Search

Max Mathew

Examiner (ID: 12068, Phone: (571)272-2378 , Office: P/2649 )

Most Active Art Unit
2649
Art Unit(s)
2644, 2649
Total Applications
304
Issued Applications
248
Pending Applications
0
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12188966 [patent_doc_number] => 20180047902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEPARATION METHOD, LIGHT-EMITTING DEVICE, MODULE, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 15/728575 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 28945 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728575 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728575
Separation method, light-emitting device, module, and electronic device Oct 9, 2017 Issued
Array ( [id] => 16536805 [patent_doc_number] => 10879422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Light emitting element [patent_app_type] => utility [patent_app_number] => 16/337851 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 10320 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337851
Light emitting element Sep 26, 2017 Issued
Array ( [id] => 12122446 [patent_doc_number] => 20180006032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'Semiconductor Devices and Fabricating Methods Thereof' [patent_app_type] => utility [patent_app_number] => 15/708512 [patent_app_country] => US [patent_app_date] => 2017-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7116 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708512 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/708512
Semiconductor devices and fabricating methods thereof Sep 18, 2017 Issued
Array ( [id] => 12223590 [patent_doc_number] => 20180061949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS' [patent_app_type] => utility [patent_app_number] => 15/701149 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701149
COMMON CONTACT OF N++ AND P++ TRANSISTOR DRAIN REGIONS IN CMOS Sep 10, 2017 Abandoned
Array ( [id] => 13085279 [patent_doc_number] => 10062713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Devices and methods for fully depleted silicon-on-insulator back biasing [patent_app_type] => utility [patent_app_number] => 15/698679 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698679
Devices and methods for fully depleted silicon-on-insulator back biasing Sep 7, 2017 Issued
Array ( [id] => 14267683 [patent_doc_number] => 10283412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor device and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/697462 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3602 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697462 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/697462
Semiconductor device and fabrication method thereof Sep 6, 2017 Issued
Array ( [id] => 12236153 [patent_doc_number] => 20180069016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => '3D MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/698523 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 64 [patent_no_of_words] => 8649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698523 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/698523
3D memory device Sep 6, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14738505 [patent_doc_number] => 10388662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Manufacturing method of semiconductor memory device [patent_app_type] => utility [patent_app_number] => 15/695892 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5812 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695892 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695892
Manufacturing method of semiconductor memory device Sep 4, 2017 Issued
Array ( [id] => 12236006 [patent_doc_number] => 20180068869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/695190 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4644 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695190
Manufacturing method for semiconductor device Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 12243169 [patent_doc_number] => 20180076032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'THICK TUNGSTEN HARDMASK FILMS DEPOSITION ON HIGH COMPRESSIVE/TENSILE BOW WAFERS' [patent_app_type] => utility [patent_app_number] => 15/695180 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695180 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695180
Thick tungsten hardmask films deposition on high compressive/tensile bow wafers Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
Array ( [id] => 14459845 [patent_doc_number] => 10325896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Microelectronics package with self-aligned stacked-die assembly [patent_app_type] => utility [patent_app_number] => 15/695629 [patent_app_country] => US [patent_app_date] => 2017-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 10479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15695629 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/695629
Microelectronics package with self-aligned stacked-die assembly Sep 4, 2017 Issued
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