Maxime M. Adjagbe

Array ( [id] => 17542804 [patent_doc_number] => 11307926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => Memory system, operation method of the same, and memory controller [patent_app_type] => utility [patent_app_number] => 16/570504 [patent_app_country] => US [patent_app_date] => 2019-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4970 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16570504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17423110 [patent_doc_number] => 11256564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-22 [patent_title] => Media quality aware ECC decoding method selection to reduce data access latency [patent_app_type] => utility [patent_app_number] => 16/565120 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 8792 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565120 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15714953 [patent_doc_number] => 20200104243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => AUTOMATED TEST COVERAGE OF COMPUTING SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/545847 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15257787 [patent_doc_number] => 20190377627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-12 [patent_title] => ROOT CAUSE ANALYSIS [patent_app_type] => utility [patent_app_number] => 16/545096 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10404 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15121071 [patent_doc_number] => 20190347169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-14 [patent_title] => REPAIRING PARTIALLY COMPLETED TRANSACTIONS IN FAST CONSENSUS PROTOCOL [patent_app_type] => utility [patent_app_number] => 16/519493 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15090553 [patent_doc_number] => 20190340087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => REPAIRING PARTIALLY COMPLETED TRANSACTIONS IN FAST CONSENSUS PROTOCOL [patent_app_type] => utility [patent_app_number] => 16/517841 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16607999 [patent_doc_number] => 10909004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-02 [patent_title] => Online system checkpoint recovery orchestration [patent_app_type] => utility [patent_app_number] => 16/511676 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16511676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16116483 [patent_doc_number] => 20200210264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SYSTEM AND METHOD OF GENERATING DATA FOR MONITORING OF A CYBER-PHYSICAL SYSTEM FOR EARLY DETERMINATION OF ANOMALIES [patent_app_type] => utility [patent_app_number] => 16/456463 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16456463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16116481 [patent_doc_number] => 20200210263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => SYSTEM AND METHOD FOR DETECTING ANOMALIES IN CYBER-PHYSICAL SYSTEM WITH DETERMINED CHARACTERISTICS [patent_app_type] => utility [patent_app_number] => 16/450195 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14510 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450195 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16527424 [patent_doc_number] => 20200401504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR CONFIGURING A TEST SYSTEM USING SOURCE CODE OF A DEVICE BEING TESTED [patent_app_type] => utility [patent_app_number] => 16/446318 [patent_app_country] => US [patent_app_date] => 2019-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15182379 [patent_doc_number] => 20190361781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => STORING MEMORY ARRAY OPERATIONAL INFORMATION IN NON-VOLATILE SUBARRAYS [patent_app_type] => utility [patent_app_number] => 16/444533 [patent_app_country] => US [patent_app_date] => 2019-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17940440 [patent_doc_number] => 11474894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Partial reroute of traffic onto a backup tunnel using predictive routing [patent_app_type] => utility [patent_app_number] => 16/429379 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18030690 [patent_doc_number] => 11513879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Detection and mitigation for solid-state storage device read failures due to weak erase [patent_app_type] => utility [patent_app_number] => 16/427502 [patent_app_country] => US [patent_app_date] => 2019-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7302 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16427502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16986977 [patent_doc_number] => 11074150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Chip health monitor [patent_app_type] => utility [patent_app_number] => 16/389049 [patent_app_country] => US [patent_app_date] => 2019-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16378197 [patent_doc_number] => 20200327039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => CROSS-THREAD MEMORY INDEXING IN TIME-TRAVEL DEBUGGING TRACES [patent_app_type] => utility [patent_app_number] => 16/387175 [patent_app_country] => US [patent_app_date] => 2019-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16387175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16378196 [patent_doc_number] => 20200327038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => MEMORY VALUE EXPOSURE IN TIME-TRAVEL DEBUGING TRACES [patent_app_type] => utility [patent_app_number] => 16/381350 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15032249 [patent_doc_number] => 20190327129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => CONNECTION CONTROL METHOD AND CONNECTION CONTROL APPARATUS [patent_app_type] => utility [patent_app_number] => 16/368164 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368164 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17076735 [patent_doc_number] => 11113134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Computer system, communications system, control method by computer system, and program [patent_app_type] => utility [patent_app_number] => 17/041097 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5577 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17041097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16879826 [patent_doc_number] => 11029973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-06-08 [patent_title] => Logic for configuring processors in a server computer [patent_app_type] => utility [patent_app_number] => 16/362244 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6188 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14585507 [patent_doc_number] => 20190220362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => EXECUTING COMPUTER INSTRUCTION INCLUDING ASYNCHRONOUS OPERATION [patent_app_type] => utility [patent_app_number] => 16/358949 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16358949 [rel_patent_id] =>[rel_patent_doc_number] =>)