M. D. I. Uddin

Array ( [id] => 1485087 [patent_doc_number] => 06453411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'System and method using a hardware embedded run-time optimizer' [patent_app_type] => B1 [patent_app_number] => 09/252170 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5439 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453411.pdf [firstpage_image] =>[orig_patent_app_number] => 09252170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4103926 [patent_doc_number] => 06026482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions' [patent_app_type] => 1 [patent_app_number] => 9/250981 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 19587 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026482.pdf [firstpage_image] =>[orig_patent_app_number] => 250981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4156135 [patent_doc_number] => 06122724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation' [patent_app_type] => 1 [patent_app_number] => 9/250922 [patent_app_country] => US [patent_app_date] => 1999-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 87 [patent_figures_cnt] => 100 [patent_no_of_words] => 39232 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122724.pdf [firstpage_image] =>[orig_patent_app_number] => 250922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1405878 [patent_doc_number] => 06560639 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'System for web content management based on server-side application' [patent_app_type] => B1 [patent_app_number] => 09/249061 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 19662 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560639.pdf [firstpage_image] =>[orig_patent_app_number] => 09249061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395753 [patent_doc_number] => 06567910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Digital signal processing unit with emulation circuitry and debug interrupt enable register indicating serviceable time-critical interrupts during real-time emulation mode' [patent_app_type] => B2 [patent_app_number] => 09/249560 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 50 [patent_no_of_words] => 31784 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567910.pdf [firstpage_image] =>[orig_patent_app_number] => 09249560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179373 [patent_doc_number] => 06115804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Non-uniform memory access (NUMA) data processing system that permits multiple caches to concurrently hold data in a recent state from which data can be sourced by shared intervention' [patent_app_type] => 1 [patent_app_number] => 9/248503 [patent_app_country] => US [patent_app_date] => 1999-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6780 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115804.pdf [firstpage_image] =>[orig_patent_app_number] => 248503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1481147 [patent_doc_number] => 06389527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Microprocessor allowing simultaneous instruction execution and DMA transfer' [patent_app_type] => B1 [patent_app_number] => 09/246406 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389527.pdf [firstpage_image] =>[orig_patent_app_number] => 09246406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4124217 [patent_doc_number] => 06101595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Fetching instructions from an instruction cache using sequential way prediction' [patent_app_type] => 1 [patent_app_number] => 9/246270 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15715 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101595.pdf [firstpage_image] =>[orig_patent_app_number] => 246270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1604530 [patent_doc_number] => 06434716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Network link tester device configured to selectively and automatically couple to a network transmit pair line or a node transmit pair line of a LAN port and determine available operational modes' [patent_app_type] => B1 [patent_app_number] => 09/240154 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7354 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434716.pdf [firstpage_image] =>[orig_patent_app_number] => 09240154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1236135 [patent_doc_number] => 06694376 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Data communication system having an interface device determining whether transmitted data to be locally processed or to be transmitted to a reception device for processing' [patent_app_type] => B1 [patent_app_number] => 09/232811 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 9163 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694376.pdf [firstpage_image] =>[orig_patent_app_number] => 09232811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4215761 [patent_doc_number] => 06014741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Apparatus and method for predicting an end of a microcode loop' [patent_app_type] => 1 [patent_app_number] => 9/233312 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014741.pdf [firstpage_image] =>[orig_patent_app_number] => 233312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4387518 [patent_doc_number] => 06275858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Intelligent method, apparatus and computer program product for automated refreshing of internet web pages' [patent_app_type] => 1 [patent_app_number] => 9/224910 [patent_app_country] => US [patent_app_date] => 1999-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4674 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275858.pdf [firstpage_image] =>[orig_patent_app_number] => 224910 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1428594 [patent_doc_number] => 06529922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Instruction set for controlling a processor to convert linear data to logarithmic data in a single instruction that define the exponent filed of the logarithmic value' [patent_app_type] => B1 [patent_app_number] => 09/219197 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7802 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529922.pdf [firstpage_image] =>[orig_patent_app_number] => 09219197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4388185 [patent_doc_number] => 06275905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Messaging scheme to maintain cache coherency and conserve system memory bandwidth during a memory read operation in a multiprocessing computer system' [patent_app_type] => 1 [patent_app_number] => 9/217649 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10324 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275905.pdf [firstpage_image] =>[orig_patent_app_number] => 217649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326196 [patent_doc_number] => 06253338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'System for tracing hardware counters utilizing programmed performance monitor to generate trace interrupt after each branch instruction or at the end of each code basic block' [patent_app_type] => 1 [patent_app_number] => 9/224121 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3263 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253338.pdf [firstpage_image] =>[orig_patent_app_number] => 224121 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177876 [patent_doc_number] => 06108764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention' [patent_app_type] => 1 [patent_app_number] => 9/213997 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5507 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108764.pdf [firstpage_image] =>[orig_patent_app_number] => 213997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152343 [patent_doc_number] => 06148361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Interrupt architecture for a non-uniform memory access (NUMA) data processing system' [patent_app_type] => 1 [patent_app_number] => 9/213998 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8785 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148361.pdf [firstpage_image] =>[orig_patent_app_number] => 213998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4278928 [patent_doc_number] => 06205468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'System for multitasking management employing context controller having event vector selection by priority encoding of contex events' [patent_app_type] => 1 [patent_app_number] => 9/213618 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14875 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205468.pdf [firstpage_image] =>[orig_patent_app_number] => 213618 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1497720 [patent_doc_number] => 06343323 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Resource retrieval over a source network determined by checking a header of the requested resource for access restrictions' [patent_app_type] => B1 [patent_app_number] => 09/213753 [patent_app_country] => US [patent_app_date] => 1998-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2517 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343323.pdf [firstpage_image] =>[orig_patent_app_number] => 09213753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1415238 [patent_doc_number] => 06549956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Mechanism for connecting disparate publication and subscribe domains via the internet' [patent_app_type] => B1 [patent_app_number] => 09/201635 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5924 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549956.pdf [firstpage_image] =>[orig_patent_app_number] => 09201635 [rel_patent_id] =>[rel_patent_doc_number] =>)