Search

Meiya Li

Examiner (ID: 5515, Phone: (571)270-1572 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1088
Issued Applications
667
Pending Applications
110
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13201937 [patent_doc_number] => 10115892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Multilayer structure for reducing film roughness in magnetic devices [patent_app_type] => utility [patent_app_number] => 15/599755 [patent_app_country] => US [patent_app_date] => 2017-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6116 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/599755
Multilayer structure for reducing film roughness in magnetic devices May 18, 2017 Issued
Array ( [id] => 16707752 [patent_doc_number] => 10957696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-23 [patent_title] => Self-aligned metal gate with poly silicide for vertical transport field-effect transistors [patent_app_type] => utility [patent_app_number] => 15/593816 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 7127 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593816
Self-aligned metal gate with poly silicide for vertical transport field-effect transistors May 11, 2017 Issued
Array ( [id] => 14064147 [patent_doc_number] => 10236379 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process [patent_app_type] => utility [patent_app_number] => 15/593651 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 8912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15593651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/593651
Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process May 11, 2017 Issued
Array ( [id] => 13543645 [patent_doc_number] => 20180323369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES [patent_app_type] => utility [patent_app_number] => 15/584294 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584294 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584294
INDUCTORS WITH THROUGH-SUBSTRATE VIA CORES May 1, 2017 Abandoned
Array ( [id] => 13543413 [patent_doc_number] => 20180323253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => SEMICONDUCTOR DEVICES WITH THROUGH-SUBSTRATE COILS FOR WIRELESS SIGNAL AND POWER COUPLING [patent_app_type] => utility [patent_app_number] => 15/584310 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584310
SEMICONDUCTOR DEVICES WITH THROUGH-SUBSTRATE COILS FOR WIRELESS SIGNAL AND POWER COUPLING May 1, 2017 Abandoned
Array ( [id] => 18639440 [patent_doc_number] => 11764060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Field-effect transistors with a body pedestal [patent_app_type] => utility [patent_app_number] => 15/584121 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3662 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584121 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584121
Field-effect transistors with a body pedestal May 1, 2017 Issued
Array ( [id] => 11840314 [patent_doc_number] => 20170222034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/491988 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2603 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491988 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491988
METHOD FOR FORMATION OF VERTICAL CYLINDRICAL GaN QUANTUM WELL TRANSISTOR Apr 19, 2017 Abandoned
Array ( [id] => 11840198 [patent_doc_number] => 20170221918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 15/491707 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5371 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491707 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491707
Nonvolatile semiconductor storage device and method of manufacture thereof Apr 18, 2017 Issued
Array ( [id] => 13500033 [patent_doc_number] => 20180301559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/489841 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489841
Semiconductor device and method of forming the same Apr 17, 2017 Issued
Array ( [id] => 16865829 [patent_doc_number] => 11024582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/489905 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489905 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489905
Semiconductor device and manufacturing method thereof Apr 17, 2017 Issued
Array ( [id] => 12027074 [patent_doc_number] => 20170317173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR SUBSTRATE, SILICON CARBIDE SEMICONDUCTOR LAYER, FIRST ELECTRODE AND SECOND ELECTRODE' [patent_app_type] => utility [patent_app_number] => 15/477186 [patent_app_country] => US [patent_app_date] => 2017-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9615 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15477186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/477186
Semiconductor device including semiconductor substrate, silicon carbide semiconductor layer, first electrode and second electrode Apr 2, 2017 Issued
Array ( [id] => 11990210 [patent_doc_number] => 20170294365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-12 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/476490 [patent_app_country] => US [patent_app_date] => 2017-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7665 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15476490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/476490
SEMICONDUCTOR DEVICE Mar 30, 2017 Abandoned
Array ( [id] => 12033789 [patent_doc_number] => 20170323888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'FINFET AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/473682 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15473682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/473682
FinFET and fabrication method thereof Mar 29, 2017 Issued
Array ( [id] => 16339271 [patent_doc_number] => 10790240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Metal line design for hybrid-bonding application [patent_app_type] => utility [patent_app_number] => 15/462078 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462078 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462078
Metal line design for hybrid-bonding application Mar 16, 2017 Issued
Array ( [id] => 18205616 [patent_doc_number] => 11588024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => High voltage blocking III-V semiconductor device [patent_app_type] => utility [patent_app_number] => 15/462019 [patent_app_country] => US [patent_app_date] => 2017-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5667 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15462019 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/462019
High voltage blocking III-V semiconductor device Mar 16, 2017 Issued
Array ( [id] => 12263941 [patent_doc_number] => 20180083137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/449329 [patent_app_country] => US [patent_app_date] => 2017-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9192 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15449329 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/449329
Semiconductor device Mar 2, 2017 Issued
Array ( [id] => 11983641 [patent_doc_number] => 20170287796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'ELECTRONIC COMPONENT PACKAGE' [patent_app_type] => utility [patent_app_number] => 15/442927 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6140 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442927 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442927
ELECTRONIC COMPONENT PACKAGE Feb 26, 2017 Abandoned
Array ( [id] => 11997669 [patent_doc_number] => 20170301824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'OPTICAL DEVICE AND METHOD FOR ITS FABRICATION' [patent_app_type] => utility [patent_app_number] => 15/442962 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442962
OPTICAL DEVICE AND METHOD FOR ITS FABRICATION Feb 26, 2017 Abandoned
Array ( [id] => 17002652 [patent_doc_number] => 11081475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Integrated circuit structure and method for reducing polymer layer delamination [patent_app_type] => utility [patent_app_number] => 15/443827 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443827 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443827
Integrated circuit structure and method for reducing polymer layer delamination Feb 26, 2017 Issued
Array ( [id] => 11946021 [patent_doc_number] => 20170250172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-31 [patent_title] => 'Semiconductor Device and Method of Stacking Semiconductor Die for System-Level ESD Protection' [patent_app_type] => utility [patent_app_number] => 15/431528 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5659 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431528 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431528
Semiconductor device and method of stacking semiconductor die for system-level ESD protection Feb 12, 2017 Issued
Menu