Search

Meiya Li

Examiner (ID: 5515, Phone: (571)270-1572 , Office: P/2811 )

Most Active Art Unit
2811
Art Unit(s)
2811
Total Applications
1088
Issued Applications
667
Pending Applications
110
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18812687 [patent_doc_number] => 20230387024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/446753 [patent_app_country] => US [patent_app_date] => 2023-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5574 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446753 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446753
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF Aug 8, 2023 Pending
Array ( [id] => 18789536 [patent_doc_number] => 20230378218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHODS FOR FORMING IMAGE SENSORS [patent_app_type] => utility [patent_app_number] => 18/366845 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19684 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366845
METHODS FOR FORMING IMAGE SENSORS Aug 7, 2023 Pending
Array ( [id] => 18821258 [patent_doc_number] => 20230395599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/230325 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230325 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230325
SEMICONDUCTOR DEVICE STRUCTURE INCLUDING FORKSHEET TRANSISTORS AND METHODS OF FORMING THE SAME Aug 3, 2023 Pending
Array ( [id] => 18791159 [patent_doc_number] => 20230380147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/364489 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364489
MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE Aug 2, 2023 Pending
Array ( [id] => 18814991 [patent_doc_number] => 20230389329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Memory Array and Methods of Forming Same [patent_app_type] => utility [patent_app_number] => 18/365068 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9244 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365068
Memory Array and Methods of Forming Same Aug 2, 2023 Pending
Array ( [id] => 19102716 [patent_doc_number] => 20240121944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/227469 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227469 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227469
SEMICONDUCTOR MEMORY DEVICE Jul 27, 2023 Pending
Array ( [id] => 20457658 [patent_doc_number] => 12520731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/357332 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 1021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357332
Memory device Jul 23, 2023 Issued
Array ( [id] => 18759687 [patent_doc_number] => 20230363176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/354768 [patent_app_country] => US [patent_app_date] => 2023-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9241 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354768 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354768
Integrated circuit and method for manufacturing the same Jul 18, 2023 Issued
Array ( [id] => 19288027 [patent_doc_number] => 20240224510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => FIELD-EFFECT TRANSISTOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/354041 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354041 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354041
FIELD-EFFECT TRANSISTOR AND INTEGRATED CIRCUIT DEVICE INCLUDING THE SAME Jul 17, 2023 Pending
Array ( [id] => 19495737 [patent_doc_number] => 12114476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Method for preparing memory array with contact enhancement sidewall spacers [patent_app_type] => utility [patent_app_number] => 18/221534 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7771 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221534
Method for preparing memory array with contact enhancement sidewall spacers Jul 12, 2023 Issued
Array ( [id] => 18776392 [patent_doc_number] => 20230371230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD FOR PREPARING MEMORY ARRAY WITH CONTACT ENHANCEMENT CAP [patent_app_type] => utility [patent_app_number] => 18/221535 [patent_app_country] => US [patent_app_date] => 2023-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18221535 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/221535
Method for preparing memory array with contact enhancement cap Jul 12, 2023 Issued
Array ( [id] => 18745598 [patent_doc_number] => 20230354592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => READ-ONLY MEMORY FOR CHIP SECURITY THAT IS MOSFET PROCESS COMPATIBLE [patent_app_type] => utility [patent_app_number] => 18/348572 [patent_app_country] => US [patent_app_date] => 2023-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4672 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348572 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348572
Read-only memory for chip security that is MOSFET process compatible Jul 6, 2023 Issued
Array ( [id] => 18729495 [patent_doc_number] => 20230343791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/216963 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216963 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216963
Display device Jun 29, 2023 Issued
Array ( [id] => 19688192 [patent_doc_number] => 20250006737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATERIALS [patent_app_type] => utility [patent_app_number] => 18/216520 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18216520 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/216520
STACKED CMOS TRANSISTOR STRUCTURES WITH COMPLEMENTARY CHANNEL MATERIALS Jun 28, 2023 Pending
Array ( [id] => 19688292 [patent_doc_number] => 20250006837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL-TRANSPORT TRANSISTOR WITH BOTTOM SOURCE CONNECTION [patent_app_type] => utility [patent_app_number] => 18/214904 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18933 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18214904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/214904
INTEGRATED CIRCUIT STRUCTURES HAVING VERTICAL-TRANSPORT TRANSISTOR WITH BOTTOM SOURCE CONNECTION Jun 26, 2023 Pending
Array ( [id] => 18714791 [patent_doc_number] => 20230337436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/338344 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18338344 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/338344
Three-dimensional memory device and manufacturing method thereof Jun 20, 2023 Issued
Array ( [id] => 18698500 [patent_doc_number] => 20230328980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/336252 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9188 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336252
Protective liner layers in 3D memory structure Jun 15, 2023 Issued
Array ( [id] => 19887017 [patent_doc_number] => 12272750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Memory array channel regions [patent_app_type] => utility [patent_app_number] => 18/330604 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 9879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330604
Memory array channel regions Jun 6, 2023 Issued
Array ( [id] => 19470506 [patent_doc_number] => 20240324176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => MEMORY DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/325008 [patent_app_country] => US [patent_app_date] => 2023-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18325008 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/325008
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF May 28, 2023 Pending
Array ( [id] => 18655261 [patent_doc_number] => 20230301112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => Memory Devices and Methods of Forming Memory Devices [patent_app_type] => utility [patent_app_number] => 18/202237 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202237 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202237
Memory devices and methods of forming memory devices May 24, 2023 Issued
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