Search

Melanie Jo Hand

Examiner (ID: 9316)

Most Active Art Unit
3761
Art Unit(s)
3761, 3778
Total Applications
1112
Issued Applications
703
Pending Applications
25
Abandoned Applications
389

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9110088 [patent_doc_number] => 20130283220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'Developing a Hardware Description Which Performs a Function by Partial Hardening of a Software Program on a Multi-Processor System' [patent_app_type] => utility [patent_app_number] => 13/862842 [patent_app_country] => US [patent_app_date] => 2013-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7736 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13862842 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/862842
Developing a hardware description which performs a function by partial hardening of a software program on a multi-processor system Apr 14, 2013 Issued
Array ( [id] => 8987098 [patent_doc_number] => 20130214380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'AREA AND POWER SAVING STANDARD CELL METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 13/859512 [patent_app_country] => US [patent_app_date] => 2013-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3545 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13859512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/859512
Area and power saving standard cell methodology Apr 8, 2013 Issued
Array ( [id] => 9006389 [patent_doc_number] => 20130227514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Method of Generating RC Technology File' [patent_app_type] => utility [patent_app_number] => 13/858760 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858760 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858760
Method of generating RC technology file Apr 7, 2013 Issued
Array ( [id] => 9695590 [patent_doc_number] => 08826220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Circuit layout method for printed circuit board, electronic device and computer readable recording media' [patent_app_type] => utility [patent_app_number] => 13/857997 [patent_app_country] => US [patent_app_date] => 2013-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9614 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857997
Circuit layout method for printed circuit board, electronic device and computer readable recording media Apr 5, 2013 Issued
Array ( [id] => 9071322 [patent_doc_number] => 20130263078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'METHOD FOR GENERATING TASK DATA OF A PCB AND INSPECTING A PCB' [patent_app_type] => utility [patent_app_number] => 13/852077 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4112 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852077 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852077
Method for generating task data of a PCB and inspecting a PCB Mar 27, 2013 Issued
Array ( [id] => 9593006 [patent_doc_number] => 08782572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-15 [patent_title] => 'Method of optical proximity correction' [patent_app_type] => utility [patent_app_number] => 13/802587 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3822 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802587 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802587
Method of optical proximity correction Mar 12, 2013 Issued
Array ( [id] => 9680678 [patent_doc_number] => 08819605 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-26 [patent_title] => 'Deriving effective corners for complex correlations' [patent_app_type] => utility [patent_app_number] => 13/786927 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786927 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786927
Deriving effective corners for complex correlations Mar 5, 2013 Issued
Array ( [id] => 8918221 [patent_doc_number] => 20130179846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'PHOTOMASK MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 13/785604 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785604 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785604
Photomask manufacturing method and semiconductor device manufacturing method Mar 4, 2013 Issued
Array ( [id] => 10834868 [patent_doc_number] => 08863064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'SRAM cell layout structure and devices therefrom' [patent_app_type] => utility [patent_app_number] => 13/776917 [patent_app_country] => US [patent_app_date] => 2013-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11922 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13776917 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/776917
SRAM cell layout structure and devices therefrom Feb 25, 2013 Issued
Array ( [id] => 9057016 [patent_doc_number] => 20130254730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'LAYOUT SYSTEM AND METHOD OF CREATING DIFFERENTIAL PAIR ON PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 13/775107 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2816 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13775107 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/775107
LAYOUT SYSTEM AND METHOD OF CREATING DIFFERENTIAL PAIR ON PRINTED CIRCUIT BOARD Feb 21, 2013 Abandoned
Array ( [id] => 9585970 [patent_doc_number] => 08775981 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-08 [patent_title] => 'Correcting for overexposure due to overlapping exposures in lithography' [patent_app_type] => utility [patent_app_number] => 13/770287 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3786 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13770287 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/770287
Correcting for overexposure due to overlapping exposures in lithography Feb 18, 2013 Issued
Array ( [id] => 9752371 [patent_doc_number] => 08843861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-23 [patent_title] => 'Third party component debugging for integrated circuit design' [patent_app_type] => utility [patent_app_number] => 13/771057 [patent_app_country] => US [patent_app_date] => 2013-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5355 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13771057 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/771057
Third party component debugging for integrated circuit design Feb 18, 2013 Issued
Array ( [id] => 9315090 [patent_doc_number] => 08656326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-18 [patent_title] => 'Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design' [patent_app_type] => utility [patent_app_number] => 13/766017 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4307 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766017 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766017
Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline design Feb 12, 2013 Issued
Array ( [id] => 8868322 [patent_doc_number] => 20130152025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'METHOD AND SYSTEM FOR COMPUTING FOURIER SERIES COEFFICIENTS FOR MASK LAYOUTS USING FFT' [patent_app_type] => utility [patent_app_number] => 13/765304 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765304 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765304
Method and system for computing fourier series coefficients for mask layouts using FFT Feb 11, 2013 Issued
Array ( [id] => 8946088 [patent_doc_number] => 08499275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Planar manufacturing drawing production support device, planar manufacturing drawing production support method, planar manufacturing drawing production support program and branch angle design support device' [patent_app_type] => utility [patent_app_number] => 13/757048 [patent_app_country] => US [patent_app_date] => 2013-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 13851 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13757048 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/757048
Planar manufacturing drawing production support device, planar manufacturing drawing production support method, planar manufacturing drawing production support program and branch angle design support device Jan 31, 2013 Issued
Array ( [id] => 10885700 [patent_doc_number] => 08910104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Graduated routing for routing electrodes coupled to touch sensor electrodes to thereby balance capacitance on the touch sensor electrodes' [patent_app_type] => utility [patent_app_number] => 13/748400 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3350 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748400 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748400
Graduated routing for routing electrodes coupled to touch sensor electrodes to thereby balance capacitance on the touch sensor electrodes Jan 22, 2013 Issued
Array ( [id] => 9458736 [patent_doc_number] => 08719763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-06 [patent_title] => 'Frequency selection with selective voltage binning' [patent_app_type] => utility [patent_app_number] => 13/733960 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5616 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733960
Frequency selection with selective voltage binning Jan 3, 2013 Issued
Array ( [id] => 9444360 [patent_doc_number] => 08713496 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Specification of latency in programmable device configuration' [patent_app_type] => utility [patent_app_number] => 13/733990 [patent_app_country] => US [patent_app_date] => 2013-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13733990 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/733990
Specification of latency in programmable device configuration Jan 3, 2013 Issued
Array ( [id] => 9821073 [patent_doc_number] => 08930876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method of debugging control flow in a stream processor' [patent_app_type] => utility [patent_app_number] => 13/725345 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 7555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725345 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725345
Method of debugging control flow in a stream processor Dec 20, 2012 Issued
Array ( [id] => 9564061 [patent_doc_number] => 20140181774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'NON-INTEGER HEIGHT STANDARD CELL LIBRARY' [patent_app_type] => utility [patent_app_number] => 13/725870 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6089 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725870 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725870
Non-integer height standard cell library Dec 20, 2012 Issued
Menu