Search

Melanie Sue Pellegrini

Examiner (ID: 11149, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2911, 2914, 2916
Total Applications
3599
Issued Applications
3478
Pending Applications
10
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20152238 [patent_doc_number] => 20250252076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SYSTOLIC ARRAY, PROCESSING CIRCUIT INCLUDING SYSTOLIC ARRAY, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 19/014441 [patent_app_country] => US [patent_app_date] => 2025-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014441 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/014441
SYSTOLIC ARRAY, PROCESSING CIRCUIT INCLUDING SYSTOLIC ARRAY, AND ELECTRONIC DEVICE Jan 8, 2025 Pending
Array ( [id] => 19891907 [patent_doc_number] => 20250117219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/988708 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18988708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/988708
NEURAL PROCESSING DEVICE, PROCESSING ELEMENT INCLUDED THEREIN AND METHOD FOR OPERATING VARIOUS FORMATS OF NEURAL PROCESSING DEVICE Dec 18, 2024 Pending
Array ( [id] => 19878479 [patent_doc_number] => 20250110736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING [patent_app_type] => utility [patent_app_number] => 18/979355 [patent_app_country] => US [patent_app_date] => 2024-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979355
PROCESSOR AND METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING Dec 11, 2024 Pending
Array ( [id] => 19864545 [patent_doc_number] => 20250103331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => PROCESSOR EMBEDDED STREAMING BUFFER [patent_app_type] => utility [patent_app_number] => 18/971447 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971447 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971447
PROCESSOR EMBEDDED STREAMING BUFFER Dec 5, 2024 Pending
Array ( [id] => 20035060 [patent_doc_number] => 20250173282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF HOST DEVICE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/960101 [patent_app_country] => US [patent_app_date] => 2024-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18960101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/960101
MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF HOST DEVICE FOR MEMORY DEVICE Nov 25, 2024 Pending
Array ( [id] => 20673187 [patent_doc_number] => 12613699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-28 [patent_title] => DMA controller and LSU to transpose data arrays stored in main memory for storage in processor registers [patent_app_type] => utility [patent_app_number] => 18/956439 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 609 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18956439 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/956439
Speeding Up Memory Access Nov 21, 2024 Issued
Array ( [id] => 19772225 [patent_doc_number] => 20250053651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => MICROARCHITECTURAL MECHANISMS FOR THE PREVENTION OF SIDE-CHANNEL ATTACKS USING A THREAD IDENTIFICATION (TID) AND A PRIVILEGE LEVEL BIT [patent_app_type] => utility [patent_app_number] => 18/925667 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925667
MICROARCHITECTURAL MECHANISMS FOR THE PREVENTION OF SIDE-CHANNEL ATTACKS USING A THREAD IDENTIFICATION (TID) AND A PRIVILEGE LEVEL BIT Oct 23, 2024 Pending
Array ( [id] => 19756486 [patent_doc_number] => 20250045051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MULTI-CARD PROCESSOR ACCESS FRAMEWORK [patent_app_type] => utility [patent_app_number] => 18/919332 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919332 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/919332
MULTI-CARD PROCESSOR ACCESS FRAMEWORK Oct 16, 2024 Pending
Array ( [id] => 19725925 [patent_doc_number] => 20250028676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => DISTRIBUTED GRAPHICS PROCESSOR UNIT ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/906534 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906534 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906534
DISTRIBUTED GRAPHICS PROCESSOR UNIT ARCHITECTURE Oct 3, 2024 Pending
Array ( [id] => 20468204 [patent_doc_number] => 12524243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Power efficient multi-bit storage system [patent_app_type] => utility [patent_app_number] => 18/886319 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886319 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/886319
Power efficient multi-bit storage system Sep 15, 2024 Issued
Array ( [id] => 19661304 [patent_doc_number] => 20240428369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => LOW LATENCY STREAMING REMAPPING ENGINE [patent_app_type] => utility [patent_app_number] => 18/828069 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18828069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/828069
LOW LATENCY STREAMING REMAPPING ENGINE Sep 8, 2024 Pending
Array ( [id] => 19603311 [patent_doc_number] => 20240394191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MULTIPLE MULTITHREADED PROCESSORS WITH SHARED DATA CACHE [patent_app_type] => utility [patent_app_number] => 18/797799 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797799 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797799
MULTIPLE MULTITHREADED PROCESSORS WITH SHARED DATA CACHE Aug 7, 2024 Pending
Array ( [id] => 19747841 [patent_doc_number] => 20250036406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => METHOD FOR EXECUTING A FUNCTION CALL, SYSTEM AND COMPUTER-READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/780313 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780313
METHOD FOR EXECUTING A FUNCTION CALL, SYSTEM AND COMPUTER-READABLE MEDIUM Jul 21, 2024 Pending
Array ( [id] => 19747845 [patent_doc_number] => 20250036410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => CLIPPING OPERATIONS USING PARTIAL CLIP INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/777537 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/777537
Clipping operations using partial clip instructions Jul 17, 2024 Issued
Array ( [id] => 19558610 [patent_doc_number] => 20240370402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Configuration Data Store in a Reconfigurable Data Processor Having Two Access Modes [patent_app_type] => utility [patent_app_number] => 18/775443 [patent_app_country] => US [patent_app_date] => 2024-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18775443 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/775443
Configuration Data Store in a Reconfigurable Data Processor Having Two Access Modes Jul 16, 2024 Pending
Array ( [id] => 20474939 [patent_doc_number] => 20260017160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => MICROPROCESSOR VALIDATION USING RANDOM PREPACKAGED GENERATED TEST FUNCTIONS AND USER LEVEL SCHEDULER [patent_app_type] => utility [patent_app_number] => 18/768239 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768239
MICROPROCESSOR VALIDATION USING RANDOM PREPACKAGED GENERATED TEST FUNCTIONS AND USER LEVEL SCHEDULER Jul 9, 2024 Pending
Array ( [id] => 20446899 [patent_doc_number] => 20260003621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Processor Employing Instruction That Performs A Bitwise Majority Vote Operation [patent_app_type] => utility [patent_app_number] => 18/759810 [patent_app_country] => US [patent_app_date] => 2024-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759810
Processor Employing Instruction That Performs A Bitwise Majority Vote Operation Jun 28, 2024 Pending
Array ( [id] => 19499259 [patent_doc_number] => 20240338277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CYCLE ACCURATE TRACING OF VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/758980 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758980
CYCLE ACCURATE TRACING OF VECTOR INSTRUCTIONS Jun 27, 2024 Pending
Array ( [id] => 20666425 [patent_doc_number] => 12608200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Computing chip and instruction processing method to access source operands in private registers using a relative distance index [patent_app_type] => utility [patent_app_number] => 18/741186 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8349 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741186
COMPUTING CHIP AND INSTRUCTION PROCESSING METHOD Jun 11, 2024 Issued
Array ( [id] => 19482194 [patent_doc_number] => 20240330236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => TWO-LEVEL ARBITRATION IN A COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 18/739272 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739272 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739272
Two-level arbitration in a computing system Jun 9, 2024 Issued
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