Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16346160 [patent_doc_number] => 20200310811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => APPARATUS AND METHOD FOR MAKING PREDICTIONS FOR INSTRUCTION FLOW CHANGING INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/364557 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16091 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364557 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364557
Apparatus and method for making predictions for instruction flow changing instructions Mar 25, 2019 Issued
Array ( [id] => 17252852 [patent_doc_number] => 11188341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => System, apparatus and method for symbolic store address generation for data-parallel processor [patent_app_type] => utility [patent_app_number] => 16/364704 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13215 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364704 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364704
System, apparatus and method for symbolic store address generation for data-parallel processor Mar 25, 2019 Issued
Array ( [id] => 16346367 [patent_doc_number] => 20200311018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => System, Apparatus And Method For Adaptive Interconnect Routing [patent_app_type] => utility [patent_app_number] => 16/364619 [patent_app_country] => US [patent_app_date] => 2019-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16364619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/364619
System, apparatus and method for adaptive interconnect routing Mar 25, 2019 Issued
Array ( [id] => 14997609 [patent_doc_number] => 20190317762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => ARITHMETIC PROCESSING UNIT AND CONTROL METHOD FOR ARITHMETIC PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 16/361281 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 463 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16361281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/361281
Arithmetic processing unit and control method for arithmetic processing unit Mar 21, 2019 Issued
Array ( [id] => 16330745 [patent_doc_number] => 20200301711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => DYNAMIC SELECTION OF OSC HAZARD AVOIDANCE MECHANISM [patent_app_type] => utility [patent_app_number] => 16/359380 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16359380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/359380
Dynamic selection of OSC hazard avoidance mechanism Mar 19, 2019 Issued
Array ( [id] => 16600104 [patent_doc_number] => 20210026635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => AN APPARATUS AND METHOD FOR CONTROLLING ALLOCATION OF INSTRUCTIONS INTO AN INSTRUCTION CACHE STORAGE [patent_app_type] => utility [patent_app_number] => 16/982300 [patent_app_country] => US [patent_app_date] => 2019-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16982300 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/982300
Apparatus and method for controlling allocation of instructions into an instruction cache storage Mar 19, 2019 Issued
Array ( [id] => 16330909 [patent_doc_number] => 20200301875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => VECTOR PROCESSOR WITH VECTOR FIRST AND MULTIPLE LANE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 16/356146 [patent_app_country] => US [patent_app_date] => 2019-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16356146 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/356146
Vector processor with vector first and multiple lane configuration Mar 17, 2019 Issued
Array ( [id] => 14539299 [patent_doc_number] => 20190205271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => COMPUTING SYSTEM WITH HARDWARE RECONFIGURATION MECHANISM AND METHOD OF OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 16/297431 [patent_app_country] => US [patent_app_date] => 2019-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16297431 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/297431
Computing system with hardware reconfiguration mechanism and method of operation thereof Mar 7, 2019 Issued
Array ( [id] => 14506727 [patent_doc_number] => 20190197018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => DYNAMIC RECONFIGURATION USING DATA TRANSFER CONTROL [patent_app_type] => utility [patent_app_number] => 16/289814 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289814
DYNAMIC RECONFIGURATION USING DATA TRANSFER CONTROL Feb 28, 2019 Abandoned
Array ( [id] => 17824607 [patent_doc_number] => 11429555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Coprocessors with bypass optimization, variable grid architecture, and fused vector operations [patent_app_type] => utility [patent_app_number] => 16/286170 [patent_app_country] => US [patent_app_date] => 2019-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15943 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16286170 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/286170
Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Feb 25, 2019 Issued
Array ( [id] => 16240413 [patent_doc_number] => 20200257647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => SYSTEM, METHOD AND APPARATUS FOR ENABLING PARTIAL DATA TRANSFERS WITH INDICATORS [patent_app_type] => utility [patent_app_number] => 16/271015 [patent_app_country] => US [patent_app_date] => 2019-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/271015
System, method and apparatus for enabling partial data transfers with indicators Feb 7, 2019 Issued
Array ( [id] => 17846793 [patent_doc_number] => 11436166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Data processing systems [patent_app_type] => utility [patent_app_number] => 16/267804 [patent_app_country] => US [patent_app_date] => 2019-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 18284 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 526 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16267804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/267804
Data processing systems Feb 4, 2019 Issued
Array ( [id] => 17744455 [patent_doc_number] => 11392525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Specialized device instantiation onto PCIe fabrics [patent_app_type] => utility [patent_app_number] => 16/265390 [patent_app_country] => US [patent_app_date] => 2019-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16265390 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/265390
Specialized device instantiation onto PCIe fabrics Jan 31, 2019 Issued
Array ( [id] => 16478192 [patent_doc_number] => 10853140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-01 [patent_title] => Slab memory allocator with dynamic buffer resizing [patent_app_type] => utility [patent_app_number] => 16/263281 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7709 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263281
Slab memory allocator with dynamic buffer resizing Jan 30, 2019 Issued
Array ( [id] => 14872691 [patent_doc_number] => 20190286587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => ASYNCHRONOUS INTERRUPT WITH SYNCHRONOUS POLLING AND INHIBIT OPTIONS ON AN RFFE BUS [patent_app_type] => utility [patent_app_number] => 16/262267 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262267 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/262267
Asynchronous interrupt with synchronous polling and inhibit options on an RFFE bus Jan 29, 2019 Issued
Array ( [id] => 16192980 [patent_doc_number] => 20200233829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => MULTI-LANE SYSTEM POWER MANAGEMENT INTERFACE [patent_app_type] => utility [patent_app_number] => 16/254189 [patent_app_country] => US [patent_app_date] => 2019-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16254189 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/254189
MULTI-LANE SYSTEM POWER MANAGEMENT INTERFACE Jan 21, 2019 Abandoned
Array ( [id] => 17487142 [patent_doc_number] => 20220094646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD AND SYSTEM FOR CENTRAL PROCESSING UNIT EFFICIENT STORING OF DATA IN A DATA CENTER [patent_app_type] => utility [patent_app_number] => 17/422912 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17422912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/422912
METHOD AND SYSTEM FOR CENTRAL PROCESSING UNIT EFFICIENT STORING OF DATA IN A DATA CENTER Jan 16, 2019 Abandoned
Array ( [id] => 20374089 [patent_doc_number] => 12481523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Flexible logic unit adapted for real-time task switching [patent_app_type] => utility [patent_app_number] => 16/958257 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6462 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16958257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/958257
Flexible logic unit adapted for real-time task switching Dec 17, 2018 Issued
Array ( [id] => 14076407 [patent_doc_number] => 20190087091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => METHOD AND DESIGN FOR DYNAMIC MANAGEMENT OF DESCRIPTORS FOR SGL OPERATION [patent_app_type] => utility [patent_app_number] => 16/181166 [patent_app_country] => US [patent_app_date] => 2018-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181166 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181166
Method and design for dynamic management of descriptors for SGL operation Nov 4, 2018 Issued
Array ( [id] => 15836779 [patent_doc_number] => 20200133672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => HYBRID AND EFFICIENT APPROACH TO ACCELERATE COMPLICATED LOOPS ON COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRA) ACCELERATORS [patent_app_type] => utility [patent_app_number] => 16/172254 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172254
HYBRID AND EFFICIENT APPROACH TO ACCELERATE COMPLICATED LOOPS ON COARSE-GRAINED RECONFIGURABLE ARRAYS (CGRA) ACCELERATORS Oct 25, 2018 Abandoned
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