Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15836791 [patent_doc_number] => 20200133678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => BRANCH PREDICTION FOR INDIRECT BRANCH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/171590 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16171590 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/171590
Branch prediction for indirect branch instructions Oct 25, 2018 Issued
Array ( [id] => 18104183 [patent_doc_number] => 11544069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Universal pointers for data exchange in a computer system having independent processors [patent_app_type] => utility [patent_app_number] => 16/170799 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170799
Universal pointers for data exchange in a computer system having independent processors Oct 24, 2018 Issued
Array ( [id] => 17572824 [patent_doc_number] => 11321092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Tensor-based memory access [patent_app_type] => utility [patent_app_number] => 16/170069 [patent_app_country] => US [patent_app_date] => 2018-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4547 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16170069 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/170069
Tensor-based memory access Oct 24, 2018 Issued
Array ( [id] => 14628855 [patent_doc_number] => 20190227795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => MICROPROCESSOR FOR NEURAL NETWORK COMPUTING AND PROCESSING METHOD OF MACROINSTRUCTION [patent_app_type] => utility [patent_app_number] => 16/163818 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163818
Microprocessor for neural network computing and processing method of macroinstruction Oct 17, 2018 Issued
Array ( [id] => 16994107 [patent_doc_number] => 20210232527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => DOCKING STATIONS TO WIRELESSLY ACCESS EDGE COMPUTE RESOURCES [patent_app_type] => utility [patent_app_number] => 17/055850 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17055850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/055850
DOCKING STATIONS TO WIRELESSLY ACCESS EDGE COMPUTE RESOURCES Oct 17, 2018 Abandoned
Array ( [id] => 15714743 [patent_doc_number] => 20200104138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => GRAPHICS ENGINE RESET AND RECOVERY IN A MULTIPLE GRAPHICS CONTEXT EXECUTION ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 16/143777 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19617 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143777 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143777
Graphics engine reset and recovery in a multiple graphics context execution environment Sep 26, 2018 Issued
Array ( [id] => 15685257 [patent_doc_number] => 20200097292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => MANAGING LOW-LEVEL INSTRUCTIONS AND CORE INTERACTIONS IN MULTI-CORE PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/140936 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140936
Managing low-level instructions and core interactions in multi-core processors Sep 24, 2018 Issued
Array ( [id] => 15685255 [patent_doc_number] => 20200097291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => APPARATUS AND METHOD FOR TILE GATHER AND TILE SCATTER [patent_app_type] => utility [patent_app_number] => 16/140196 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140196 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140196
APPARATUS AND METHOD FOR TILE GATHER AND TILE SCATTER Sep 23, 2018 Abandoned
Array ( [id] => 15685265 [patent_doc_number] => 20200097296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => PROVIDING LATE PHYSICAL REGISTER ALLOCATION AND EARLY PHYSICAL REGISTER RELEASE IN OUT-OF-ORDER PROCESSOR (OOP)-BASED DEVICES IMPLEMENTING A CHECKPOINT-BASED ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/138011 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138011
Providing late physical register allocation and early physical register release in out-of-order processor (OOP)-based devices implementing a checkpoint-based architecture Sep 20, 2018 Issued
Array ( [id] => 15654205 [patent_doc_number] => 20200089633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => ADJUSTING INTERRUPT PRIORITIES [patent_app_type] => utility [patent_app_number] => 16/133554 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/133554
Adjusting interrupt priorities Sep 16, 2018 Issued
Array ( [id] => 14570807 [patent_doc_number] => 20190213010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => PROCESSOR DEVICE COLLECTING PERFORMANCE INFORMATION THROUGH COMMAND-SET-BASED REPLAY [patent_app_type] => utility [patent_app_number] => 16/132784 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/132784
Processor device collecting performance information through command-set-based replay Sep 16, 2018 Issued
Array ( [id] => 15027867 [patent_doc_number] => 20190324938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => METHOD FOR HOT-PLUGGING IDENTIFICATION AND SERVER WITH FUNCTION OF HOT-PLUGGING IDENTIFICATION [patent_app_type] => utility [patent_app_number] => 16/128722 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128722
METHOD FOR HOT-PLUGGING IDENTIFICATION AND SERVER WITH FUNCTION OF HOT-PLUGGING IDENTIFICATION Sep 11, 2018 Abandoned
Array ( [id] => 14218765 [patent_doc_number] => 20190121767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => IN-BAND RESET AND WAKE UP ON A DIFFERENTIAL AUDIO BUS [patent_app_type] => utility [patent_app_number] => 16/119127 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5827 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119127 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/119127
IN-BAND RESET AND WAKE UP ON A DIFFERENTIAL AUDIO BUS Aug 30, 2018 Abandoned
Array ( [id] => 17309135 [patent_doc_number] => 11210246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Probe interrupt delivery [patent_app_type] => utility [patent_app_number] => 16/112367 [patent_app_country] => US [patent_app_date] => 2018-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112367 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/112367
Probe interrupt delivery Aug 23, 2018 Issued
Array ( [id] => 15561751 [patent_doc_number] => 20200065287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => NETWORKING SYSTEMS USING MULTIPLE PERIPHERAL COMPONENT CARDS [patent_app_type] => utility [patent_app_number] => 16/107014 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107014
NETWORKING SYSTEMS USING MULTIPLE PERIPHERAL COMPONENT CARDS Aug 20, 2018 Abandoned
Array ( [id] => 16431417 [patent_doc_number] => 10831499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Apparatus and method for performing branch prediction [patent_app_type] => utility [patent_app_number] => 16/106382 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11030 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16106382 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/106382
Apparatus and method for performing branch prediction Aug 20, 2018 Issued
Array ( [id] => 16462740 [patent_doc_number] => 10846088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Control of instruction execution in a data processor [patent_app_type] => utility [patent_app_number] => 16/107250 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 13545 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107250 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107250
Control of instruction execution in a data processor Aug 20, 2018 Issued
Array ( [id] => 17786407 [patent_doc_number] => 11409530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => System, method and apparatus for executing instructions [patent_app_type] => utility [patent_app_number] => 16/103995 [patent_app_country] => US [patent_app_date] => 2018-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6530 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16103995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/103995
System, method and apparatus for executing instructions Aug 15, 2018 Issued
Array ( [id] => 13933695 [patent_doc_number] => 20190050363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => ELECTRONIC DEVICE, LOGIC CHIP AND COMMUNICATION METHOD OF LOGIC CHIP [patent_app_type] => utility [patent_app_number] => 16/102762 [patent_app_country] => US [patent_app_date] => 2018-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/102762
ELECTRONIC DEVICE, LOGIC CHIP AND COMMUNICATION METHOD OF LOGIC CHIP Aug 13, 2018 Abandoned
Array ( [id] => 18046759 [patent_doc_number] => 11520713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-06 [patent_title] => Distributed bus arbiter for one-cycle channel selection using inter-channel ordering constraints in a disaggregated memory system [patent_app_type] => utility [patent_app_number] => 16/054698 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8334 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054698 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054698
Distributed bus arbiter for one-cycle channel selection using inter-channel ordering constraints in a disaggregated memory system Aug 2, 2018 Issued
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