Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12034507 [patent_doc_number] => 20170324606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'SERIAL COMMUNICATIONS TAP DEVICE' [patent_app_type] => utility [patent_app_number] => 15/590529 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3345 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590529 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590529
SERIAL COMMUNICATIONS TAP DEVICE May 8, 2017 Abandoned
Array ( [id] => 12053388 [patent_doc_number] => 20170329732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'METHOD FOR TEMPORALLY SYNCHRONIZING THE OUTPUT AND/OR TEMPORALLY SYNCHRONIZING THE PROCESSING OF SIGNALS' [patent_app_type] => utility [patent_app_number] => 15/586798 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8894 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586798
METHOD FOR TEMPORALLY SYNCHRONIZING THE OUTPUT AND/OR TEMPORALLY SYNCHRONIZING THE PROCESSING OF SIGNALS May 3, 2017 Abandoned
Array ( [id] => 13497225 [patent_doc_number] => 20180300155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => MANAGEMENT OF STORE QUEUE BASED ON RESTORATION OPERATION [patent_app_type] => utility [patent_app_number] => 15/489989 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489989 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489989
Management of store queue based on restoration operation Apr 17, 2017 Issued
Array ( [id] => 12161126 [patent_doc_number] => 20180032392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'DATA BUS INVERSION CONTROLLER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/487930 [patent_app_country] => US [patent_app_date] => 2017-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5870 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487930 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487930
DATA BUS INVERSION CONTROLLER AND SEMICONDUCTOR DEVICE INCLUDING THE SAME Apr 13, 2017 Abandoned
Array ( [id] => 12735079 [patent_doc_number] => 20180136860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/471525 [patent_app_country] => US [patent_app_date] => 2017-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15471525 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/471525
SEMICONDUCTOR MEMORY DEVICE Mar 27, 2017 Abandoned
Array ( [id] => 12666001 [patent_doc_number] => 20180113833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => BOARD MANAGEMENT CONTROLLER PERIPHERAL CARD, HOST SYSTEM WITH THE SAME, AND METHOD FOR MANAGING HOST PERIPHERAL MEMBER BY THE SAME [patent_app_type] => utility [patent_app_number] => 15/470233 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470233 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470233
BOARD MANAGEMENT CONTROLLER PERIPHERAL CARD, HOST SYSTEM WITH THE SAME, AND METHOD FOR MANAGING HOST PERIPHERAL MEMBER BY THE SAME Mar 26, 2017 Abandoned
Array ( [id] => 15854967 [patent_doc_number] => 10642769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Serial peripheral interface daisy chain mode system and apparatus [patent_app_type] => utility [patent_app_number] => 15/468781 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6171 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468781
Serial peripheral interface daisy chain mode system and apparatus Mar 23, 2017 Issued
Array ( [id] => 11981572 [patent_doc_number] => 20170285726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'MULTIFUNCTION PERIPHERAL DEVICE INCLUDING PERIPHERAL COMPONENT INTERCONNECT (PCI) DEVICE CONNECTED TO PCI BUS, INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/469255 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11005 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469255
MULTIFUNCTION PERIPHERAL DEVICE INCLUDING PERIPHERAL COMPONENT INTERCONNECT (PCI) DEVICE CONNECTED TO PCI BUS, INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, AND STORAGE MEDIUM Mar 23, 2017 Abandoned
Array ( [id] => 13448343 [patent_doc_number] => 20180275714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => INDUCTIVE COUPLING FOR DATA COMMUNICATION IN A DOUBLE DATA RATE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 15/468310 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468310
INDUCTIVE COUPLING FOR DATA COMMUNICATION IN A DOUBLE DATA RATE MEMORY SYSTEM Mar 23, 2017 Abandoned
Array ( [id] => 13449257 [patent_doc_number] => 20180276171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-27 [patent_title] => NON-VOLATILE MEMORY DRIVES [patent_app_type] => utility [patent_app_number] => 15/468022 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15468022 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/468022
NON-VOLATILE MEMORY DRIVES Mar 22, 2017 Abandoned
Array ( [id] => 14953015 [patent_doc_number] => 10437772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Addressing of slave devices on a single wire communications bus through register map address selection [patent_app_type] => utility [patent_app_number] => 15/467790 [patent_app_country] => US [patent_app_date] => 2017-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8870 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15467790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/467790
Addressing of slave devices on a single wire communications bus through register map address selection Mar 22, 2017 Issued
Array ( [id] => 12735736 [patent_doc_number] => 20180137079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => INTER-INTEGRATED CIRCUIT BUS ARBITRATION SYSTEM CAPABLE OF AVOIDING HOST CONFLICT [patent_app_type] => utility [patent_app_number] => 15/466823 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/466823
Inter-integrated circuit bus arbitration system capable of avoiding host conflict Mar 21, 2017 Issued
Array ( [id] => 12869068 [patent_doc_number] => 20180181531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => SERIAL PERIPHERAL MODE IN MIPI IMPROVED INTER-INTEGRATED CIRCUIT (I3C) [patent_app_type] => utility [patent_app_number] => 15/466315 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/466315
SERIAL PERIPHERAL MODE IN MIPI IMPROVED INTER-INTEGRATED CIRCUIT (I3C) Mar 21, 2017 Abandoned
Array ( [id] => 13948429 [patent_doc_number] => 10209989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Accelerated interlane vector reduction instructions [patent_app_type] => utility [patent_app_number] => 15/452479 [patent_app_country] => US [patent_app_date] => 2017-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 9298 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15452479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/452479
Accelerated interlane vector reduction instructions Mar 6, 2017 Issued
Array ( [id] => 14669097 [patent_doc_number] => 10372449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-06 [patent_title] => Packed data operation mask concatenation processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 15/442823 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 17578 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442823
Packed data operation mask concatenation processors, methods, systems, and instructions Feb 26, 2017 Issued
Array ( [id] => 11621977 [patent_doc_number] => 20170132164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Unified Extensible Firmware Interface System Management Mode Initialization Protections with System Management Interrupt Transfer Monitor Sandboxing' [patent_app_type] => utility [patent_app_number] => 15/414152 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15414152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/414152
Unified Extensible Firmware Interface System Management Mode Initialization Protections with System Management Interrupt Transfer Monitor Sandboxing Jan 23, 2017 Abandoned
Array ( [id] => 14966971 [patent_doc_number] => 20190310964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => SPECULATIVE READ MECHANISM FOR DISTRIBUTED STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/346842 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16346842 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/346842
SPECULATIVE READ MECHANISM FOR DISTRIBUTED STORAGE SYSTEM Dec 27, 2016 Abandoned
Array ( [id] => 11437950 [patent_doc_number] => 20170038971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'MEMORY CONTROLLER AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/297466 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6922 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297466
Memory controller and memory system Oct 18, 2016 Issued
Array ( [id] => 11570516 [patent_doc_number] => 20170109160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'INSTRUCTION FOR PERFORMING AN OVERLOAD CHECK' [patent_app_type] => utility [patent_app_number] => 15/238703 [patent_app_country] => US [patent_app_date] => 2016-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4476 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15238703 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/238703
Instruction for performing an overload check Aug 15, 2016 Issued
Array ( [id] => 13665007 [patent_doc_number] => 10162665 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-25 [patent_title] => Hypervisor assisted control of CPU access to externally managed physical memory [patent_app_type] => utility [patent_app_number] => 15/214822 [patent_app_country] => US [patent_app_date] => 2016-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7780 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15214822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/214822
Hypervisor assisted control of CPU access to externally managed physical memory Jul 19, 2016 Issued
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