Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11397063 [patent_doc_number] => 20170017599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'METHOD FOR COMMUNICATION BETWEEN A SENSOR AND A CONNECTING ELEMENT' [patent_app_type] => utility [patent_app_number] => 15/210951 [patent_app_country] => US [patent_app_date] => 2016-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3754 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15210951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/210951
Method for communication between a sensor and a connecting element Jul 14, 2016 Issued
Array ( [id] => 11672505 [patent_doc_number] => 20170161227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'UNIVERSAL SERIAL BUS CONVERTER CIRCUIT AND RELATED METHOD' [patent_app_type] => utility [patent_app_number] => 15/209764 [patent_app_country] => US [patent_app_date] => 2016-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2689 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15209764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/209764
Universal serial bus converter circuit and related method Jul 13, 2016 Issued
Array ( [id] => 11494445 [patent_doc_number] => 20170068629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'SEMICONDUCTOR APPARATUS AND STATUS CONTROL METHOD OF SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/208262 [patent_app_country] => US [patent_app_date] => 2016-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10870 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15208262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/208262
SEMICONDUCTOR APPARATUS AND STATUS CONTROL METHOD OF SEMICONDUCTOR APPARATUS Jul 11, 2016 Abandoned
Array ( [id] => 13281705 [patent_doc_number] => 10152437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 15/205682 [patent_app_country] => US [patent_app_date] => 2016-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8762 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15205682 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/205682
Memory system Jul 7, 2016 Issued
Array ( [id] => 12128227 [patent_doc_number] => 20180011813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-11 [patent_title] => 'SERIAL MID-SPEED INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/202910 [patent_app_country] => US [patent_app_date] => 2016-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14752 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15202910 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/202910
SERIAL MID-SPEED INTERFACE Jul 5, 2016 Abandoned
Array ( [id] => 12121102 [patent_doc_number] => 20180004688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'LOAD REDUCED NONVOLATILE MEMORY INTERFACE' [patent_app_type] => utility [patent_app_number] => 15/201370 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15259 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15201370 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/201370
Load reduced nonvolatile memory interface Jun 30, 2016 Issued
Array ( [id] => 11445277 [patent_doc_number] => 20170046298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'ASYNCHRONOUS FIRST-IN FIRST-OUT BUFFER APPARATUS WITH ACTIVE RATE CONTROL AND DYNAMIC RATE COMPENSATION AND ASSOCIATED NETWORK DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/199914 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15199914 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/199914
ASYNCHRONOUS FIRST-IN FIRST-OUT BUFFER APPARATUS WITH ACTIVE RATE CONTROL AND DYNAMIC RATE COMPENSATION AND ASSOCIATED NETWORK DEVICE USING THE SAME Jun 29, 2016 Abandoned
Array ( [id] => 13068911 [patent_doc_number] => 10055235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Device management apparatus, device management system, and device management method [patent_app_type] => utility [patent_app_number] => 15/171034 [patent_app_country] => US [patent_app_date] => 2016-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8045 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15171034 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/171034
Device management apparatus, device management system, and device management method Jun 1, 2016 Issued
Array ( [id] => 13891679 [patent_doc_number] => 10198387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Electronic device and method for controlling signal strength according to mode [patent_app_type] => utility [patent_app_number] => 15/163310 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15163310 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/163310
Electronic device and method for controlling signal strength according to mode May 23, 2016 Issued
Array ( [id] => 12495594 [patent_doc_number] => 09996483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => N-base numbers to physical wire states symbols translation method [patent_app_type] => utility [patent_app_number] => 15/092554 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18825 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092554
N-base numbers to physical wire states symbols translation method Apr 5, 2016 Issued
Array ( [id] => 10991549 [patent_doc_number] => 20160188493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'INFORMATION PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/064066 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13075 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064066 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/064066
Information processing apparatus Mar 7, 2016 Issued
Array ( [id] => 11064462 [patent_doc_number] => 20160261426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'STATIC DATA BUS ADDRESS ALLOCATION' [patent_app_type] => utility [patent_app_number] => 15/061010 [patent_app_country] => US [patent_app_date] => 2016-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7658 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15061010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/061010
Static data bus address allocation Mar 3, 2016 Issued
Array ( [id] => 10786174 [patent_doc_number] => 20160132330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'INSTRUCTION AND LOGIC FOR BOYER-MOORE SEARCH OF TEXT STRINGS' [patent_app_type] => utility [patent_app_number] => 14/997417 [patent_app_country] => US [patent_app_date] => 2016-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 20353 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997417
Instruction and logic for Boyer-Moore search of text strings Jan 14, 2016 Issued
Array ( [id] => 13948581 [patent_doc_number] => 10210066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Instruction and logic to test transactional execution status [patent_app_type] => utility [patent_app_number] => 14/998047 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 14198 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998047 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998047
Instruction and logic to test transactional execution status Dec 23, 2015 Issued
Array ( [id] => 14175727 [patent_doc_number] => 10261879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Instruction and logic to test transactional execution status [patent_app_type] => utility [patent_app_number] => 14/757919 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 14198 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757919 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757919
Instruction and logic to test transactional execution status Dec 23, 2015 Issued
Array ( [id] => 11070028 [patent_doc_number] => 20160266992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'Instruction and logic to test transactional execution status' [patent_app_type] => utility [patent_app_number] => 14/998055 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14644 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998055 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998055
Instruction and logic to test transactional execution status Dec 23, 2015 Issued
Array ( [id] => 11006038 [patent_doc_number] => 20160202987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'Instruction and logic to test transactional execution status' [patent_app_type] => utility [patent_app_number] => 14/757980 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 14186 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14757980 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/757980
Instruction and logic to test transactional execution status Dec 23, 2015 Issued
Array ( [id] => 14009537 [patent_doc_number] => 10223227 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Instruction and logic to test transactional execution status [patent_app_type] => utility [patent_app_number] => 14/998052 [patent_app_country] => US [patent_app_date] => 2015-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 14198 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998052 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/998052
Instruction and logic to test transactional execution status Dec 23, 2015 Issued
Array ( [id] => 13281633 [patent_doc_number] => 10152401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Instruction and logic to test transactional execution status [patent_app_type] => utility [patent_app_number] => 14/977659 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 14183 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977659 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977659
Instruction and logic to test transactional execution status Dec 21, 2015 Issued
Array ( [id] => 11665230 [patent_doc_number] => 20170153949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'Switching Allocation of Computer Bus Lanes' [patent_app_type] => utility [patent_app_number] => 14/955766 [patent_app_country] => US [patent_app_date] => 2015-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6778 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955766 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/955766
Switching allocation of computer bus lanes Nov 30, 2015 Issued
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