Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11314137 [patent_doc_number] => 20160350247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'LATENCY IMPROVEMENTS ON A BUS USING MODIFIED TRANSFERS' [patent_app_type] => utility [patent_app_number] => 14/750603 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5390 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750603 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750603
LATENCY IMPROVEMENTS ON A BUS USING MODIFIED TRANSFERS Jun 24, 2015 Abandoned
Array ( [id] => 10724762 [patent_doc_number] => 20160070910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'PLATFORM BASED VERIFICATION OF CONTENTS OF INPUT-OUTPUT DEVICES' [patent_app_type] => utility [patent_app_number] => 14/739968 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3557 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739968 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739968
PLATFORM BASED VERIFICATION OF CONTENTS OF INPUT-OUTPUT DEVICES Jun 14, 2015 Abandoned
Array ( [id] => 10408856 [patent_doc_number] => 20150293865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'Restore PCIe Transaction ID On The Fly' [patent_app_type] => utility [patent_app_number] => 14/728676 [patent_app_country] => US [patent_app_date] => 2015-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4255 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14728676 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/728676
Restore PCIe Transaction ID On The Fly Jun 1, 2015 Abandoned
Array ( [id] => 11550562 [patent_doc_number] => 09619411 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Polling determination' [patent_app_type] => utility [patent_app_number] => 14/723015 [patent_app_country] => US [patent_app_date] => 2015-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2963 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14723015 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/723015
Polling determination May 26, 2015 Issued
Array ( [id] => 11056311 [patent_doc_number] => 20160253273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-01 [patent_title] => 'HUB, OPERATION SYSTEM, AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/700507 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700507 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700507
HUB, OPERATION SYSTEM, AND CONTROL METHOD THEREOF Apr 29, 2015 Abandoned
Array ( [id] => 14364641 [patent_doc_number] => 10303626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Approach for chip-level flop insertion and verification based on logic interface definition [patent_app_type] => utility [patent_app_number] => 14/675342 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4823 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675342
Approach for chip-level flop insertion and verification based on logic interface definition Mar 30, 2015 Issued
Array ( [id] => 11094899 [patent_doc_number] => 20160291867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD AND DESIGN FOR DYNAMIC MANAGEMENT OF DESCRIPTORS FOR SGL OPERATION' [patent_app_type] => utility [patent_app_number] => 14/674739 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14674739 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/674739
Method and design for dynamic management of descriptors for SGL operation Mar 30, 2015 Issued
Array ( [id] => 12249117 [patent_doc_number] => 09921891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-20 [patent_title] => 'Low latency interconnect integrated event handling' [patent_app_type] => utility [patent_app_number] => 14/675498 [patent_app_country] => US [patent_app_date] => 2015-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7086 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14675498 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/675498
Low latency interconnect integrated event handling Mar 30, 2015 Issued
Array ( [id] => 11095147 [patent_doc_number] => 20160292115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems' [patent_app_type] => utility [patent_app_number] => 14/673724 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673724 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673724
Methods and Apparatus for IO, Processing and Memory Bandwidth Optimization for Analytics Systems Mar 29, 2015 Abandoned
Array ( [id] => 12011659 [patent_doc_number] => 09804978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Memory system facilitating high bandwidth and high capacity memory' [patent_app_type] => utility [patent_app_number] => 14/672709 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 8060 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672709 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672709
Memory system facilitating high bandwidth and high capacity memory Mar 29, 2015 Issued
Array ( [id] => 14555751 [patent_doc_number] => 10346337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Offload pipeline for data mirroring [patent_app_type] => utility [patent_app_number] => 14/673466 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673466
Offload pipeline for data mirroring Mar 29, 2015 Issued
Array ( [id] => 11095148 [patent_doc_number] => 20160292117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'Methods and Apparatus for Efficient Network Analytics and Computing Card' [patent_app_type] => utility [patent_app_number] => 14/673818 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3322 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673818 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673818
Methods and Apparatus for Efficient Network Analytics and Computing Card Mar 29, 2015 Abandoned
Array ( [id] => 10393136 [patent_doc_number] => 20150278143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-01 [patent_title] => 'Method And Device For Connecting USB Port And Method For Transmitting Data' [patent_app_type] => utility [patent_app_number] => 14/671165 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7016 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671165 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671165
Method And Device For Connecting USB Port And Method For Transmitting Data Mar 26, 2015 Abandoned
Array ( [id] => 11086462 [patent_doc_number] => 20160283428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'METHOD, APPARATUS AND SYSTEM TO IMPLEMENT SECONDARY BUS FUNCTIONALITY VIA A RECONFIGURABLE VIRTUAL SWITCH' [patent_app_type] => utility [patent_app_number] => 14/669256 [patent_app_country] => US [patent_app_date] => 2015-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9383 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14669256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/669256
Method, apparatus and system to implement secondary bus functionality via a reconfigurable virtual switch Mar 25, 2015 Issued
Array ( [id] => 10301130 [patent_doc_number] => 20150186131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'METHOD AND APPARATUS FOR FIELD FIRMWARE UPDATES IN DATA STORAGE SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/645106 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4061 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645106 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/645106
Method and apparatus for field firmware updates in data storage systems Mar 10, 2015 Issued
Array ( [id] => 10293230 [patent_doc_number] => 20150178229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'COMPUTER SYSTEM AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/632043 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 14117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14632043 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/632043
Computer system and control method thereof Feb 25, 2015 Issued
Array ( [id] => 12114342 [patent_doc_number] => 09870336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Implementing sideband control structure for PCIE cable cards and IO expansion enclosures' [patent_app_type] => utility [patent_app_number] => 14/628203 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6473 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14628203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/628203
Implementing sideband control structure for PCIE cable cards and IO expansion enclosures Feb 19, 2015 Issued
Array ( [id] => 11042500 [patent_doc_number] => 20160239456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'ELECTRONIC DEVICE FOR COMMUNICATING BETWEEN A MICROCONTROLLER UNIT (MCU) AND A HOST PROCESSOR AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/625196 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14625196 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/625196
Electronic device for communicating between a microcontroller unit (MCU) and a host processor and related methods Feb 17, 2015 Issued
Array ( [id] => 10357346 [patent_doc_number] => 20150242351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'STORAGE SYSTEM, CONTROL APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/624610 [patent_app_country] => US [patent_app_date] => 2015-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9965 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624610 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624610
STORAGE SYSTEM, CONTROL APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM Feb 17, 2015 Abandoned
Array ( [id] => 11042501 [patent_doc_number] => 20160239458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'DEVICES WITH ASYMMETRIC SAS GENERATION SUPPORT' [patent_app_type] => utility [patent_app_number] => 14/624333 [patent_app_country] => US [patent_app_date] => 2015-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3602 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14624333 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/624333
Devices with asymmetric SAS generation support Feb 16, 2015 Issued
Menu