Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19963679 [patent_doc_number] => 12333188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Bandwidth balancing for a single namespace tenant in multi-function nonvolatile memory express devices [patent_app_type] => utility [patent_app_number] => 18/351351 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351351
Bandwidth balancing for a single namespace tenant in multi-function nonvolatile memory express devices Jul 11, 2023 Issued
Array ( [id] => 19036527 [patent_doc_number] => 20240086342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 18/215036 [patent_app_country] => US [patent_app_date] => 2023-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18215036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/215036
Semiconductor system Jun 26, 2023 Issued
Array ( [id] => 20095155 [patent_doc_number] => 20250225091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => METHOD AND RELATED APPARATUS FOR PCIE DATA TRANSMISSION [patent_app_type] => utility [patent_app_number] => 18/850546 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18850546 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/850546
METHOD AND RELATED APPARATUS FOR PCIE DATA TRANSMISSION May 21, 2023 Pending
Array ( [id] => 19573883 [patent_doc_number] => 20240378175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => MULTI-CHIP SYSTOLIC ARRAYS [patent_app_type] => utility [patent_app_number] => 18/195769 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6718 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -38 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18195769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/195769
MULTI-CHIP SYSTOLIC ARRAYS May 9, 2023 Pending
Array ( [id] => 19841927 [patent_doc_number] => 12254318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Speculative register reclamation [patent_app_type] => utility [patent_app_number] => 18/143990 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 13083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143990 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143990
Speculative register reclamation May 4, 2023 Issued
Array ( [id] => 18725334 [patent_doc_number] => 20230339499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => DISTRIBUTED COMPUTING ARCHITECTURE WITH SHARED MEMORY FOR AUTONOMOUS ROBOTIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/139857 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16240 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139857
DISTRIBUTED COMPUTING ARCHITECTURE WITH SHARED MEMORY FOR AUTONOMOUS ROBOTIC SYSTEMS Apr 25, 2023 Pending
Array ( [id] => 19950495 [patent_doc_number] => 12321861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Initialization of parameters for machine-learned transformer neural network architectures [patent_app_type] => utility [patent_app_number] => 18/303179 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303179 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/303179
Initialization of parameters for machine-learned transformer neural network architectures Apr 18, 2023 Issued
Array ( [id] => 18513218 [patent_doc_number] => 20230229446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => SYSTEMS AND METHODS TO LOAD A TILE REGISTER PAIR [patent_app_type] => utility [patent_app_number] => 18/186710 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18186710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/186710
Systems and methods to load a tile register pair Mar 19, 2023 Issued
Array ( [id] => 18839380 [patent_doc_number] => 11847454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-19 [patent_title] => Solid-state microwave source and branch consistency control method thereof [patent_app_type] => utility [patent_app_number] => 18/116297 [patent_app_country] => US [patent_app_date] => 2023-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18116297 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/116297
Solid-state microwave source and branch consistency control method thereof Feb 28, 2023 Issued
Array ( [id] => 18654155 [patent_doc_number] => 20230300001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/174387 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174387
PROCESSING SYSTEM, RELATED INTEGRATED CIRCUIT, DEVICE AND METHOD Feb 23, 2023 Pending
Array ( [id] => 20035087 [patent_doc_number] => 20250173309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => DIE-TO-DIE DENSE PACKAGING OF DETERMINISTIC STREAMING PROCESSORS [patent_app_type] => utility [patent_app_number] => 18/840368 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18840368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/840368
DIE-TO-DIE DENSE PACKAGING OF DETERMINISTIC STREAMING PROCESSORS Feb 20, 2023 Pending
Array ( [id] => 18568760 [patent_doc_number] => 20230259096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => METHOD FOR GENERATING A TWIN SENSOR BY WAY OF PARAMETER INHERITANCE [patent_app_type] => utility [patent_app_number] => 18/168966 [patent_app_country] => US [patent_app_date] => 2023-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/168966
METHOD FOR GENERATING A TWIN SENSOR BY WAY OF PARAMETER INHERITANCE Feb 13, 2023 Pending
Array ( [id] => 20145588 [patent_doc_number] => 12379930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Prediction using unified predictor circuitry [patent_app_type] => utility [patent_app_number] => 18/106560 [patent_app_country] => US [patent_app_date] => 2023-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 7912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18106560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/106560
Prediction using unified predictor circuitry Feb 6, 2023 Issued
Array ( [id] => 20117441 [patent_doc_number] => 12367147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Padding and suppressing rows and columns of data [patent_app_type] => utility [patent_app_number] => 18/165196 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 50 [patent_no_of_words] => 30856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165196 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/165196
Padding and suppressing rows and columns of data Feb 5, 2023 Issued
Array ( [id] => 19427173 [patent_doc_number] => 12086596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Instructions for accelerating Keccak execution in a processor [patent_app_type] => utility [patent_app_number] => 18/164738 [patent_app_country] => US [patent_app_date] => 2023-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 15551 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164738
Instructions for accelerating Keccak execution in a processor Feb 5, 2023 Issued
Array ( [id] => 19992741 [patent_doc_number] => 20250130963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => DATA PROCESSING METHOD, APPARATUS AND SYSTEM BASED ON PARA-VIRTUALIZATION DEVICE [patent_app_type] => utility [patent_app_number] => 18/685110 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18685110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/685110
DATA PROCESSING METHOD, APPARATUS AND SYSTEM BASED ON PARA-VIRTUALIZATION DEVICE Feb 2, 2023 Issued
Array ( [id] => 18379492 [patent_doc_number] => 20230154581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => GATEWAY CONFORMANCE VALIDATION [patent_app_type] => utility [patent_app_number] => 18/099781 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099781
Gateway conformance validation Jan 19, 2023 Issued
Array ( [id] => 20265777 [patent_doc_number] => 12436768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Universal pointers for data exchange in a computer system having independent processors [patent_app_type] => utility [patent_app_number] => 18/148701 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148701
Universal pointers for data exchange in a computer system having independent processors Dec 29, 2022 Issued
Array ( [id] => 18213798 [patent_doc_number] => 20230060064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => APPARATUS INCLUDING PARALLEL PIPELINES AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/979679 [patent_app_country] => US [patent_app_date] => 2022-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17979679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/979679
Apparatus including parallel pipelines and methods of manufacturing the same Nov 1, 2022 Issued
Array ( [id] => 18312874 [patent_doc_number] => 20230116774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => LOAD REDUCED NONVOLATILE MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 17/971201 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971201
Load reduced nonvolatile memory interface Oct 20, 2022 Issued
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