Search

Melanie Sue Pellegrini

Examiner (ID: 13920, Phone: (571)272-6028 , Office: P/2911 )

Most Active Art Unit
2911
Art Unit(s)
2914, 2916, 2911
Total Applications
3599
Issued Applications
3477
Pending Applications
11
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17401680 [patent_doc_number] => 20220043770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => NEURAL NETWORK PROCESSOR, CHIP AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/452058 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19552 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452058
NEURAL NETWORK PROCESSOR, CHIP AND ELECTRONIC DEVICE Oct 21, 2021 Abandoned
Array ( [id] => 19677713 [patent_doc_number] => 12189569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-07 [patent_title] => Distributive training with multicast [patent_app_type] => utility [patent_app_number] => 17/449300 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449300
Distributive training with multicast Sep 28, 2021 Issued
Array ( [id] => 17853926 [patent_doc_number] => 20220283968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => METHOD OF SYNCHRONIZING TIME BETWEEN HOST DEVICE AND STORAGE DEVICE AND SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/477784 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477784 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477784
Method of synchronizing time between host device and storage device and system performing the same Sep 16, 2021 Issued
Array ( [id] => 17706805 [patent_doc_number] => 20220206811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => METHOD AND SYSTEM FOR EXECUTING NEW INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 17/471454 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471454
Method and system for executing new instructions Sep 9, 2021 Issued
Array ( [id] => 19872624 [patent_doc_number] => 12265484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Processing device and method of sharing storage between cache memory, local data storage and register files [patent_app_type] => utility [patent_app_number] => 17/467104 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5134 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467104 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467104
Processing device and method of sharing storage between cache memory, local data storage and register files Sep 2, 2021 Issued
Array ( [id] => 19212294 [patent_doc_number] => 12001356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Delay elements for command timing in a memory device [patent_app_type] => utility [patent_app_number] => 17/463318 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7795 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463318 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463318
Delay elements for command timing in a memory device Aug 30, 2021 Issued
Array ( [id] => 18839002 [patent_doc_number] => 11847073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Data path interface circuit, memory and memory system [patent_app_type] => utility [patent_app_number] => 17/446571 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7448 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446571
Data path interface circuit, memory and memory system Aug 30, 2021 Issued
Array ( [id] => 17293743 [patent_doc_number] => 20210389582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => ENDOSCOPE MOTHERBOARD, ENDOSCOPE AND DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/446232 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446232 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446232
ENDOSCOPE MOTHERBOARD, ENDOSCOPE AND DETECTION METHOD Aug 26, 2021 Abandoned
Array ( [id] => 17261100 [patent_doc_number] => 20210374085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => MODULAR SYSTEM ARCHITECTURE FOR SUPPORTING MULTIPLE SOLID-STATE DRIVES [patent_app_type] => utility [patent_app_number] => 17/405770 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405770
Modular system architecture for supporting multiple solid-state drives Aug 17, 2021 Issued
Array ( [id] => 18053068 [patent_doc_number] => 11526453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-13 [patent_title] => Apparatus including parallel pipelines and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/401729 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14711 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401729 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401729
Apparatus including parallel pipelines and methods of manufacturing the same Aug 12, 2021 Issued
Array ( [id] => 17484344 [patent_doc_number] => 20220091848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SYSTEMS AND METHODS TO LOAD A TILE REGISTER PAIR [patent_app_type] => utility [patent_app_number] => 17/398927 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398927
Systems and methods to load a tile register pair Aug 9, 2021 Issued
Array ( [id] => 18197664 [patent_doc_number] => 20230051183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => APPARATUS INCLUDING RECONFIGURABLE INTERFACE AND METHODS OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/398863 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398863
Apparatus including reconfigurable interface and methods of manufacturing the same Aug 9, 2021 Issued
Array ( [id] => 19062168 [patent_doc_number] => 11941404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Processor and method for controlling the processor [patent_app_type] => utility [patent_app_number] => 17/375574 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 15665 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375574
Processor and method for controlling the processor Jul 13, 2021 Issued
Array ( [id] => 17447367 [patent_doc_number] => 20220067872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => GRAPHICS PROCESSING UNIT INCLUDING DELEGATOR AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/372851 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372851
Graphics processing unit including delegator and operating method thereof Jul 11, 2021 Issued
Array ( [id] => 18262177 [patent_doc_number] => 11609879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Techniques for configuring parallel processors for different application domains [patent_app_type] => utility [patent_app_number] => 17/365315 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 16581 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365315
Techniques for configuring parallel processors for different application domains Jun 30, 2021 Issued
Array ( [id] => 18925529 [patent_doc_number] => 20240028533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => AUTOMATED DESIGN OF BEHAVIORAL-BASED DATA MOVERS FOR FIELD PROGRAMMABLE GATE ARRAYS OR OTHER LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/364481 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/364481
Automated design of behavioral-based data movers for field programmable gate arrays or other logic devices Jun 29, 2021 Issued
Array ( [id] => 17172611 [patent_doc_number] => 20210326281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => APPARATUS AND METHODS FOR IN DATA PATH COMPUTE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/360388 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360388 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360388
Apparatus and methods for in data path compute operations Jun 27, 2021 Issued
Array ( [id] => 18095583 [patent_doc_number] => 20220413924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 17/358542 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/358542
Using sparsity metadata to reduce systolic array power consumption Jun 24, 2021 Issued
Array ( [id] => 18662492 [patent_doc_number] => 20230308514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => INPUT UNIT, CONTROL SYSTEM, COMMUNICATION METHOD, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/035517 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035517 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/035517
INPUT UNIT, CONTROL SYSTEM, COMMUNICATION METHOD, AND RECORDING MEDIUM Jun 24, 2021 Abandoned
Array ( [id] => 17597790 [patent_doc_number] => 20220147364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/338870 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/338870
SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM Jun 3, 2021 Abandoned
Menu