Search

Melody Noel Brown

Examiner (ID: 13321, Phone: (571)272-2599 , Office: P/2917 )

Most Active Art Unit
2917
Art Unit(s)
2915, 2901, 2917, 2911
Total Applications
11867
Issued Applications
11761
Pending Applications
2
Abandoned Applications
102

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19219870 [patent_doc_number] => 20240184574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => Stateful Vector Group Permutation with Storage Reuse [patent_app_type] => utility [patent_app_number] => 18/524149 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524149
Stateful vector group permutation with storage reuse Nov 29, 2023 Issued
Array ( [id] => 19204722 [patent_doc_number] => 20240176621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/519590 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519590 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/519590
PROCESSOR Nov 26, 2023 Pending
Array ( [id] => 19219877 [patent_doc_number] => 20240184581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => BIT PATTERN MATCHING HARDWARE PREFETCHER [patent_app_type] => utility [patent_app_number] => 18/497170 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9816 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497170 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/497170
BIT PATTERN MATCHING HARDWARE PREFETCHER Oct 29, 2023 Pending
Array ( [id] => 18990085 [patent_doc_number] => 20240062054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => STORAGE OF INPUT VALUES ACROSS MULTIPLE CORES OF NEURAL NETWORK INFERENCE CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/384576 [patent_app_country] => US [patent_app_date] => 2023-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18384576 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/384576
STORAGE OF INPUT VALUES ACROSS MULTIPLE CORES OF NEURAL NETWORK INFERENCE CIRCUIT Oct 26, 2023 Pending
Array ( [id] => 19267564 [patent_doc_number] => 20240211267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MULTI-PROCESSOR DEVICE, DATA PROCESSING SYSTEM AND PERIPHERAL CONTROLLER SHARING METHOD [patent_app_type] => utility [patent_app_number] => 18/494044 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4603 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494044
MULTI-PROCESSOR DEVICE, DATA PROCESSING SYSTEM AND PERIPHERAL CONTROLLER SHARING METHOD Oct 24, 2023 Pending
Array ( [id] => 19144623 [patent_doc_number] => 20240143540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SYSTEM ON CHIP AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/494152 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11319 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494152 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494152
SYSTEM ON CHIP AND METHOD OF OPERATING THE SAME Oct 24, 2023 Pending
Array ( [id] => 18957349 [patent_doc_number] => 20240045676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => Execution or Write Mask Generation for Data Selection in a Multi-Threaded, Self-Scheduling Reconfigurable Computing Fabric [patent_app_type] => utility [patent_app_number] => 18/377804 [patent_app_country] => US [patent_app_date] => 2023-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18377804 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/377804
Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric Oct 7, 2023 Issued
Array ( [id] => 19129296 [patent_doc_number] => 20240134649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INSTRUCTION COMPRESSION METHOD, INSTRUCTION DECOMPRESSION METHOD AND PROCESS COMPRESSION METHOD [patent_app_type] => utility [patent_app_number] => 18/376454 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376454
INSTRUCTION COMPRESSION METHOD, INSTRUCTION DECOMPRESSION METHOD AND PROCESS COMPRESSION METHOD Oct 3, 2023 Pending
Array ( [id] => 19129296 [patent_doc_number] => 20240134649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => INSTRUCTION COMPRESSION METHOD, INSTRUCTION DECOMPRESSION METHOD AND PROCESS COMPRESSION METHOD [patent_app_type] => utility [patent_app_number] => 18/376454 [patent_app_country] => US [patent_app_date] => 2023-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18376454 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/376454
INSTRUCTION COMPRESSION METHOD, INSTRUCTION DECOMPRESSION METHOD AND PROCESS COMPRESSION METHOD Oct 2, 2023 Pending
Array ( [id] => 19864556 [patent_doc_number] => 20250103342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => METHOD AND APPARATUS FOR ENABLING MIMD-LIKE EXECUTION FLOW ON SIMD PROCESSING ARRAY SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/475918 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475918
METHOD AND APPARATUS FOR ENABLING MIMD-LIKE EXECUTION FLOW ON SIMD PROCESSING ARRAY SYSTEMS Sep 26, 2023 Pending
Array ( [id] => 19864554 [patent_doc_number] => 20250103340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => SYSTEMS AND METHODS FOR RESYNCHRONIZATION AT EXECUTION TIME [patent_app_type] => utility [patent_app_number] => 18/475507 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475507 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/475507
SYSTEMS AND METHODS FOR RESYNCHRONIZATION AT EXECUTION TIME Sep 26, 2023 Pending
Array ( [id] => 19434587 [patent_doc_number] => 20240303085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => PROCESSOR ARCHITECTURE FOR OPTIMIZED PARALLELIZED SEARCH [patent_app_type] => utility [patent_app_number] => 18/474728 [patent_app_country] => US [patent_app_date] => 2023-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474728 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474728
PROCESSOR ARCHITECTURE FOR OPTIMIZED PARALLELIZED SEARCH Sep 25, 2023 Pending
Array ( [id] => 18897164 [patent_doc_number] => 20240012649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => INSTRUCTION CONVERSION METHOD, INSTRUCTION CONVERSION SYSTEM, AND PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/474207 [patent_app_country] => US [patent_app_date] => 2023-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18474207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/474207
INSTRUCTION CONVERSION METHOD, INSTRUCTION CONVERSION SYSTEM, AND PROCESSOR Sep 24, 2023 Pending
Array ( [id] => 18897159 [patent_doc_number] => 20240012644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => EFFICIENT DIRECT CONVOLUTION USING SIMD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/472482 [patent_app_country] => US [patent_app_date] => 2023-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18472482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/472482
EFFICIENT DIRECT CONVOLUTION USING SIMD INSTRUCTIONS Sep 21, 2023 Pending
Array ( [id] => 18881298 [patent_doc_number] => 20240004667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => PARALLEL PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/369532 [patent_app_country] => US [patent_app_date] => 2023-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369532
PARALLEL PROCESSING DEVICE Sep 17, 2023 Pending
Array ( [id] => 19756526 [patent_doc_number] => 20250045091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => LOW LATENCY INTER CORE COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/364037 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12613 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364037 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/364037
LOW LATENCY INTER CORE COMMUNICATION Aug 1, 2023 Abandoned
Array ( [id] => 18772771 [patent_doc_number] => 20230367597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR [patent_app_type] => utility [patent_app_number] => 18/227608 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10559 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18227608 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/227608
INSTRUCTION HANDLING FOR ACCUMULATION OF REGISTER RESULTS IN A MICROPROCESSOR Jul 27, 2023 Pending
Array ( [id] => 19747848 [patent_doc_number] => 20250036413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => Measuring Performance Associated with Processing Instructions [patent_app_type] => utility [patent_app_number] => 18/357984 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357984 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/357984
Measuring Performance Associated with Processing Instructions Jul 23, 2023 Pending
Array ( [id] => 20265775 [patent_doc_number] => 12436766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Sharing branch predictor resource for instruction cache and trace cache predictions [patent_app_type] => utility [patent_app_number] => 18/352351 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 14256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352351 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352351
Sharing branch predictor resource for instruction cache and trace cache predictions Jul 13, 2023 Issued
Array ( [id] => 18741695 [patent_doc_number] => 20230350676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => Tensor Processing Method, Apparatus, and Device, and Computer-Readable Storage Medium [patent_app_type] => utility [patent_app_number] => 18/350907 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350907 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350907
Tensor Processing Method, Apparatus, and Device, and Computer-Readable Storage Medium Jul 11, 2023 Pending
Menu