
Melody Noel Brown
Examiner (ID: 13321, Phone: (571)272-2599 , Office: P/2917 )
| Most Active Art Unit | 2917 |
| Art Unit(s) | 2915, 2901, 2917, 2911 |
| Total Applications | 11867 |
| Issued Applications | 11761 |
| Pending Applications | 2 |
| Abandoned Applications | 102 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17499370
[patent_doc_number] => 11288076
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-29
[patent_title] => IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory
[patent_app_type] => utility
[patent_app_number] => 17/019212
[patent_app_country] => US
[patent_app_date] => 2020-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 31
[patent_no_of_words] => 15666
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 416
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019212
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/019212 | IC including logic tile, having reconfigurable MAC pipeline, and reconfigurable memory | Sep 11, 2020 | Issued |
Array
(
[id] => 16722168
[patent_doc_number] => 20210089315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-25
[patent_title] => SYSTEM, DEVICE, AND METHOD FOR PROCESSING INSTRUCTIONS BASED ON MULTIPLE LEVELS OF BRANCH TARGET BUFFERS
[patent_app_type] => utility
[patent_app_number] => 16/994052
[patent_app_country] => US
[patent_app_date] => 2020-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8661
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994052
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/994052 | Moving entries between multiple levels of a branch predictor based on a performance loss resulting from fewer than a pre-set number of instructions being stored in an instruction cache register | Aug 13, 2020 | Issued |
Array
(
[id] => 16630358
[patent_doc_number] => 20210049011
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => UNIVERSAL FLOATING-POINT INSTRUCTION SET ARCHITECTURE FOR COMPUTING DIRECTLY WITH DECIMAL CHARACTER SEQUENCES AND BINARY FORMATS IN ANY COMBINATION
[patent_app_type] => utility
[patent_app_number] => 16/943077
[patent_app_country] => US
[patent_app_date] => 2020-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 49877
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943077
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/943077 | Universal floating-point instruction set architecture for computing directly with decimal character sequences and binary formats in any combination | Jul 29, 2020 | Issued |
Array
(
[id] => 17372104
[patent_doc_number] => 20220027156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => PERFORMANCE OPTIMIZATION OF CLOSE CODE
[patent_app_type] => utility
[patent_app_number] => 16/934247
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934247
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/934247 | PERFORMANCE OPTIMIZATION OF CLOSE CODE | Jul 20, 2020 | Abandoned |
Array
(
[id] => 16577326
[patent_doc_number] => 20210011727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => STM32 LOWPOWER SMART CACHE PREFETCH
[patent_app_type] => utility
[patent_app_number] => 16/922095
[patent_app_country] => US
[patent_app_date] => 2020-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2840
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922095
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/922095 | STM32 LOWPOWER SMART CACHE PREFETCH | Jul 6, 2020 | Pending |
Array
(
[id] => 16577315
[patent_doc_number] => 20210011716
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => PROCESSING CIRCUIT, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/914514
[patent_app_country] => US
[patent_app_date] => 2020-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914514
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914514 | PROCESSING CIRCUIT, INFORMATION PROCESSING APPARATUS, AND INFORMATION PROCESSING METHOD | Jun 28, 2020 | Abandoned |
Array
(
[id] => 17316967
[patent_doc_number] => 20210406016
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => MATRIX DATA SCATTER AND GATHER BY ROW
[patent_app_type] => utility
[patent_app_number] => 16/914321
[patent_app_country] => US
[patent_app_date] => 2020-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27341
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914321
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914321 | Matrix data scatter and gather between rows and irregularly spaced memory locations | Jun 26, 2020 | Issued |
Array
(
[id] => 18189299
[patent_doc_number] => 11579884
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Instruction address translation and caching for primary and alternate branch prediction paths
[patent_app_type] => utility
[patent_app_number] => 16/913520
[patent_app_country] => US
[patent_app_date] => 2020-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4594
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913520
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/913520 | Instruction address translation and caching for primary and alternate branch prediction paths | Jun 25, 2020 | Issued |
Array
(
[id] => 17301613
[patent_doc_number] => 20210397452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => VIRTUAL 3-WAY DECOUPLED PREDICTION AND FETCH
[patent_app_type] => utility
[patent_app_number] => 16/909352
[patent_app_country] => US
[patent_app_date] => 2020-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6388
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909352
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/909352 | Virtual 3-way decoupled prediction and fetch | Jun 22, 2020 | Issued |
Array
(
[id] => 19493425
[patent_doc_number] => 12112141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-08
[patent_title] => Accelerating 2D convolutional layer mapping on a dot product architecture
[patent_app_type] => utility
[patent_app_number] => 16/900819
[patent_app_country] => US
[patent_app_date] => 2020-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 27
[patent_no_of_words] => 9776
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 406
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16900819
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/900819 | Accelerating 2D convolutional layer mapping on a dot product architecture | Jun 11, 2020 | Issued |
Array
(
[id] => 17294109
[patent_doc_number] => 20210389948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => MIXED-ELEMENT-SIZE INSTRUCTION
[patent_app_type] => utility
[patent_app_number] => 16/897483
[patent_app_country] => US
[patent_app_date] => 2020-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14125
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897483
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/897483 | MIXED-ELEMENT-SIZE INSTRUCTION | Jun 9, 2020 | Abandoned |
Array
(
[id] => 16780122
[patent_doc_number] => 20210117201
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => MULTIPORTED PARITY SCOREBOARD CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 16/888604
[patent_app_country] => US
[patent_app_date] => 2020-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13100
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888604
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/888604 | Multiported parity scoreboard circuit | May 28, 2020 | Issued |
Array
(
[id] => 18234801
[patent_doc_number] => 11599359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Methods and systems for utilizing a master-shadow physical register file based on verified activation
[patent_app_type] => utility
[patent_app_number] => 16/877112
[patent_app_country] => US
[patent_app_date] => 2020-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 17110
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16877112
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/877112 | Methods and systems for utilizing a master-shadow physical register file based on verified activation | May 17, 2020 | Issued |
Array
(
[id] => 16543288
[patent_doc_number] => 20200409703
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => METHODS, DEVICES, AND MEDIA FOR PROCESSING LOOP INSTRUCTION SET
[patent_app_type] => utility
[patent_app_number] => 15/931486
[patent_app_country] => US
[patent_app_date] => 2020-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5665
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15931486
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/931486 | METHODS, DEVICES, AND MEDIA FOR PROCESSING LOOP INSTRUCTION SET | May 12, 2020 | Abandoned |
Array
(
[id] => 16400902
[patent_doc_number] => 20200341760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-29
[patent_title] => DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND READ/ADVANCE OPERAND CODING
[patent_app_type] => utility
[patent_app_number] => 16/871253
[patent_app_country] => US
[patent_app_date] => 2020-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18504
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16871253
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/871253 | Data processing apparatus having streaming engine with read and read/advance operand coding | May 10, 2020 | Issued |
Array
(
[id] => 17269159
[patent_doc_number] => 11194584
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-12-07
[patent_title] => Managing out-of-order retirement of instructions
[patent_app_type] => utility
[patent_app_number] => 16/862703
[patent_app_country] => US
[patent_app_date] => 2020-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 10343
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16862703
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/862703 | Managing out-of-order retirement of instructions | Apr 29, 2020 | Issued |
Array
(
[id] => 17187257
[patent_doc_number] => 20210334142
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-28
[patent_title] => SYSTOLIC ARRAY-FRIENDLY DATA PLACEMENT AND CONTROL
[patent_app_type] => utility
[patent_app_number] => 16/857797
[patent_app_country] => US
[patent_app_date] => 2020-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11010
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16857797
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/857797 | Systolic array-friendly data placement and control based on masked write | Apr 23, 2020 | Issued |
Array
(
[id] => 16378098
[patent_doc_number] => 20200326940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-15
[patent_title] => DATA LOADING AND STORAGE INSTRUCTION PROCESSING METHOD AND DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/845828
[patent_app_country] => US
[patent_app_date] => 2020-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11065
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16845828
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/845828 | DATA LOADING AND STORAGE INSTRUCTION PROCESSING METHOD AND DEVICE | Apr 9, 2020 | Abandoned |
Array
(
[id] => 17690561
[patent_doc_number] => 20220197854
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => Reconfigurable System-On-Chip
[patent_app_type] => utility
[patent_app_number] => 17/603896
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603896
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/603896 | Reconfigurable System-On-Chip | Apr 8, 2020 | Pending |
Array
(
[id] => 17158771
[patent_doc_number] => 20210319822
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => Deep Learning Accelerator and Random Access Memory with Separate Memory Access Connections
[patent_app_type] => utility
[patent_app_number] => 16/844993
[patent_app_country] => US
[patent_app_date] => 2020-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10071
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16844993
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/844993 | Deep learning accelerator and random access memory with separate memory access connections | Apr 8, 2020 | Issued |