Search

Melvin C. Marcelo

Examiner (ID: 7963, Phone: (571)272-3125 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2616, 2603, 2663, 2607, 2416, 2739, 2712, 2463, 2733, 2662
Total Applications
2145
Issued Applications
1788
Pending Applications
206
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9891563 [patent_doc_number] => 08977838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-10 [patent_title] => 'Architecture for cooperating hierarchical microcoded compute engines' [patent_app_type] => utility [patent_app_number] => 12/896123 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 6567 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12896123 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/896123
Architecture for cooperating hierarchical microcoded compute engines Sep 30, 2010 Issued
Array ( [id] => 8097859 [patent_doc_number] => 20120084537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-05 [patent_title] => 'SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/894762 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2934 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20120084537.pdf [firstpage_image] =>[orig_patent_app_number] => 12894762 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/894762
SYSTEM AND METHOD FOR EXECUTION BASED FILTERING OF INSTRUCTIONS OF A PROCESSOR TO MANAGE DYNAMIC CODE OPTIMIZATION Sep 29, 2010 Abandoned
Array ( [id] => 9416835 [patent_doc_number] => 08700887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Register, processor, and method of controlling a processor using data type information' [patent_app_type] => utility [patent_app_number] => 12/895366 [patent_app_country] => US [patent_app_date] => 2010-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4947 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12895366 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/895366
Register, processor, and method of controlling a processor using data type information Sep 29, 2010 Issued
Array ( [id] => 8059031 [patent_doc_number] => 20120079249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Training Decode Unit for Previously-Detected Instruction Type' [patent_app_type] => utility [patent_app_number] => 12/892438 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7025 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079249.pdf [firstpage_image] =>[orig_patent_app_number] => 12892438 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892438
Training Decode Unit for Previously-Detected Instruction Type Sep 27, 2010 Abandoned
Array ( [id] => 5981600 [patent_doc_number] => 20110072244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'Credit-Based Streaming Multiprocessor Warp Scheduling' [patent_app_type] => utility [patent_app_number] => 12/885299 [patent_app_country] => US [patent_app_date] => 2010-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072244.pdf [firstpage_image] =>[orig_patent_app_number] => 12885299 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/885299
Credit-based streaming multiprocessor warp scheduling Sep 16, 2010 Issued
Array ( [id] => 7819863 [patent_doc_number] => 20120066483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Computing Device with Asynchronous Auxiliary Execution Unit' [patent_app_type] => utility [patent_app_number] => 12/882434 [patent_app_country] => US [patent_app_date] => 2010-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9118 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066483.pdf [firstpage_image] =>[orig_patent_app_number] => 12882434 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/882434
Computing device with asynchronous auxiliary execution unit Sep 14, 2010 Issued
Array ( [id] => 6125350 [patent_doc_number] => 20110078418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Support for Non-Local Returns in Parallel Thread SIMD Engine' [patent_app_type] => utility [patent_app_number] => 12/881065 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8250 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20110078418.pdf [firstpage_image] =>[orig_patent_app_number] => 12881065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881065
Support for non-local returns in parallel thread SIMD engine Sep 12, 2010 Issued
Array ( [id] => 5982271 [patent_doc_number] => 20110072438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'FAST MAPPING TABLE REGISTER FILE ALLOCATION ALGORITHM FOR SIMT PROCESSORS' [patent_app_type] => utility [patent_app_number] => 12/875944 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9893 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20110072438.pdf [firstpage_image] =>[orig_patent_app_number] => 12875944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875944
Fast mapping table register file allocation algorithm for SIMT processors Sep 2, 2010 Issued
Array ( [id] => 11509121 [patent_doc_number] => 09600281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Matrix multiplication operations using pair-wise load and splat operations' [patent_app_type] => utility [patent_app_number] => 12/834464 [patent_app_country] => US [patent_app_date] => 2010-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 37 [patent_no_of_words] => 24777 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12834464 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/834464
Matrix multiplication operations using pair-wise load and splat operations Jul 11, 2010 Issued
Array ( [id] => 9077443 [patent_doc_number] => 08555035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-08 [patent_title] => 'Conflict-free register allocation using a multi-bank register file with input operand alignment' [patent_app_type] => utility [patent_app_number] => 12/831953 [patent_app_country] => US [patent_app_date] => 2010-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 10228 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12831953 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/831953
Conflict-free register allocation using a multi-bank register file with input operand alignment Jul 6, 2010 Issued
Array ( [id] => 6100430 [patent_doc_number] => 20110004741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'Spilling Method in Register Files for Microprocessor' [patent_app_type] => utility [patent_app_number] => 12/829711 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2162 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004741.pdf [firstpage_image] =>[orig_patent_app_number] => 12829711 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829711
Spilling method involving register files based on communication costs and use ratio Jul 1, 2010 Issued
Array ( [id] => 7714164 [patent_doc_number] => 20120005457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'USING SOFTWARE-CONTROLLED SMT PRIORITY TO OPTIMIZE DATA PREFETCH WITH ASSIST THREAD' [patent_app_type] => utility [patent_app_number] => 12/828326 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6233 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005457.pdf [firstpage_image] =>[orig_patent_app_number] => 12828326 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/828326
USING SOFTWARE-CONTROLLED SMT PRIORITY TO OPTIMIZE DATA PREFETCH WITH ASSIST THREAD Jun 30, 2010 Abandoned
Array ( [id] => 6140606 [patent_doc_number] => 20110010528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-13 [patent_title] => 'INFORMATION PROCESSING DEVICE AND VECTOR INFORMATION PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/829146 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6201 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20110010528.pdf [firstpage_image] =>[orig_patent_app_number] => 12829146 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829146
INFORMATION PROCESSING DEVICE AND VECTOR INFORMATION PROCESSING DEVICE Jun 30, 2010 Abandoned
Array ( [id] => 7714171 [patent_doc_number] => 20120005462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Hardware Assist for Optimizing Code During Processing' [patent_app_type] => utility [patent_app_number] => 12/828697 [patent_app_country] => US [patent_app_date] => 2010-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 13406 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005462.pdf [firstpage_image] =>[orig_patent_app_number] => 12828697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/828697
Hardware Assist for Optimizing Code During Processing Jun 30, 2010 Abandoned
Array ( [id] => 6362772 [patent_doc_number] => 20100332803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'PROCESSOR AND CONTROL METHOD FOR PROCESSOR' [patent_app_type] => utility [patent_app_number] => 12/827238 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 15643 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0332/20100332803.pdf [firstpage_image] =>[orig_patent_app_number] => 12827238 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/827238
Extended register addressing using prefix instruction Jun 29, 2010 Issued
Array ( [id] => 6100431 [patent_doc_number] => 20110004742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-06 [patent_title] => 'Variable-Cycle, Event-Driven Multi-Execution Flash Processor' [patent_app_type] => utility [patent_app_number] => 12/826949 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3304 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20110004742.pdf [firstpage_image] =>[orig_patent_app_number] => 12826949 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826949
Variable-Cycle, Event-Driven Multi-Execution Flash Processor Jun 29, 2010 Abandoned
Array ( [id] => 6008861 [patent_doc_number] => 20110060892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'SPECULATIVE FORWARDING OF NON-ARCHITECTED DATA FORMAT FLOATING POINT RESULTS' [patent_app_type] => utility [patent_app_number] => 12/820662 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2899 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20110060892.pdf [firstpage_image] =>[orig_patent_app_number] => 12820662 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/820662
SPECULATIVE FORWARDING OF NON-ARCHITECTED DATA FORMAT FLOATING POINT RESULTS Jun 21, 2010 Abandoned
Array ( [id] => 7664994 [patent_doc_number] => 20110314263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-22 [patent_title] => 'INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND' [patent_app_type] => utility [patent_app_number] => 12/820768 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 25977 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12820768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/820768
INSTRUCTIONS FOR PERFORMING AN OPERATION ON TWO OPERANDS AND SUBSEQUENTLY STORING AN ORIGINAL VALUE OF OPERAND Jun 21, 2010 Abandoned
Array ( [id] => 9847644 [patent_doc_number] => 08949577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Performing a deterministic reduction operation in a parallel computer' [patent_app_type] => utility [patent_app_number] => 12/789986 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10024 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789986 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789986
Performing a deterministic reduction operation in a parallel computer May 27, 2010 Issued
Array ( [id] => 7588579 [patent_doc_number] => 20110283090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'Instruction Addressing Using Register Address Sequence Detection' [patent_app_type] => utility [patent_app_number] => 12/778635 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6131 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20110283090.pdf [firstpage_image] =>[orig_patent_app_number] => 12778635 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778635
Instruction operand addressing using register address sequence detection May 11, 2010 Issued
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