Search

Melvin C. Marcelo

Examiner (ID: 7963, Phone: (571)272-3125 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2616, 2603, 2663, 2607, 2416, 2739, 2712, 2463, 2733, 2662
Total Applications
2145
Issued Applications
1788
Pending Applications
206
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9919173 [patent_doc_number] => 20150074378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'System and Method for an Asynchronous Processor with Heterogeneous Processors' [patent_app_type] => utility [patent_app_number] => 14/480541 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3790 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480541 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480541
System and method for an asynchronous processor with heterogeneous processors Sep 7, 2014 Issued
Array ( [id] => 9919474 [patent_doc_number] => 20150074680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR WITH A TOKEN RING BASED PARALLEL PROCESSOR SCHEDULER' [patent_app_type] => utility [patent_app_number] => 14/480561 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480561 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480561
METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR WITH A TOKEN RING BASED PARALLEL PROCESSOR SCHEDULER Sep 7, 2014 Abandoned
Array ( [id] => 11816928 [patent_doc_number] => 09720880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-01 [patent_title] => 'System and method for an asynchronous processor with assisted token' [patent_app_type] => utility [patent_app_number] => 14/480562 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 4906 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480562 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480562
System and method for an asynchronous processor with assisted token Sep 7, 2014 Issued
Array ( [id] => 9919174 [patent_doc_number] => 20150074379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'System and Method for an Asynchronous Processor with Token-Based Very Long Instruction Word Architecture' [patent_app_type] => utility [patent_app_number] => 14/480035 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3968 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480035
System and method for an asynchronous processor with token-based very long instruction word architecture Sep 7, 2014 Issued
Array ( [id] => 13041011 [patent_doc_number] => 10042641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor [patent_app_type] => utility [patent_app_number] => 14/480573 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14480573 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/480573
Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor Sep 7, 2014 Issued
Array ( [id] => 14427003 [patent_doc_number] => 10318305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => System and method for an asynchronous processor with pepelined arithmetic and logic unit [patent_app_type] => utility [patent_app_number] => 14/477536 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3057 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477536 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477536
System and method for an asynchronous processor with pepelined arithmetic and logic unit Sep 3, 2014 Issued
Array ( [id] => 9933814 [patent_doc_number] => 20150082006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'System and Method for an Asynchronous Processor with Asynchronous Instruction Fetch, Decode, and Issue' [patent_app_type] => utility [patent_app_number] => 14/477563 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477563 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477563
System and Method for an Asynchronous Processor with Asynchronous Instruction Fetch, Decode, and Issue Sep 3, 2014 Abandoned
Array ( [id] => 10210631 [patent_doc_number] => 20150095622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'APPARATUS AND METHOD FOR CONTROLLING EXECUTION OF PROCESSES IN A PARALLEL COMPUTING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/475961 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10774 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475961 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475961
Apparatus and method for controlling execution of processes in a parallel computing system Sep 2, 2014 Issued
Array ( [id] => 9919148 [patent_doc_number] => 20150074353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'System and Method for an Asynchronous Processor with Multiple Threading' [patent_app_type] => utility [patent_app_number] => 14/476535 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4199 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476535 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/476535
System and Method for an Asynchronous Processor with Multiple Threading Sep 2, 2014 Abandoned
Array ( [id] => 11810822 [patent_doc_number] => 09715392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Multiple clustered very long instruction word processing core' [patent_app_type] => utility [patent_app_number] => 14/473947 [patent_app_country] => US [patent_app_date] => 2014-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6977 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14473947 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/473947
Multiple clustered very long instruction word processing core Aug 28, 2014 Issued
Array ( [id] => 11584726 [patent_doc_number] => 09639368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Branch prediction based on correlating events' [patent_app_type] => utility [patent_app_number] => 14/303758 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 24 [patent_no_of_words] => 14730 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303758 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/303758
Branch prediction based on correlating events Jun 12, 2014 Issued
Array ( [id] => 12352083 [patent_doc_number] => 09952870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-24 [patent_title] => Apparatus and method for bias-free branch prediction [patent_app_type] => utility [patent_app_number] => 14/303932 [patent_app_country] => US [patent_app_date] => 2014-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5032 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14303932 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/303932
Apparatus and method for bias-free branch prediction Jun 12, 2014 Issued
Array ( [id] => 10969703 [patent_doc_number] => 20140372736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'DATA PROCESSING APPARATUS AND METHOD FOR HANDLING RETRIEVAL OF INSTRUCTIONS FROM AN INSTRUCTION CACHE' [patent_app_type] => utility [patent_app_number] => 14/301991 [patent_app_country] => US [patent_app_date] => 2014-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301991 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301991
Instruction prefetch throttling using instruction count and branch prediction Jun 10, 2014 Issued
Array ( [id] => 11278691 [patent_doc_number] => 09495170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall' [patent_app_type] => utility [patent_app_number] => 14/102807 [patent_app_country] => US [patent_app_date] => 2013-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10241 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14102807 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/102807
Determining each stall reason for each stalled instruction within a group of instructions during a pipeline stall Dec 10, 2013 Issued
Array ( [id] => 9398430 [patent_doc_number] => 20140095836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'CROSS-PIPE SERIALIZATION FOR MULTI-PIPELINE PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/101622 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5159 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101622 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/101622
Cross-pipe serialization for multi-pipeline processor Dec 9, 2013 Issued
Array ( [id] => 9398442 [patent_doc_number] => 20140095848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'Tracking Operand Liveliness Information in a Computer System and Performing Function Based on the Liveliness Information' [patent_app_type] => utility [patent_app_number] => 14/100077 [patent_app_country] => US [patent_app_date] => 2013-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/100077
Tracking operand liveness information in a computer system and performing function based on the liveness information Dec 8, 2013 Issued
Array ( [id] => 9372466 [patent_doc_number] => 20140082339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'GLOBAL WEAK PATTERN HISTORY TABLE FILTERING' [patent_app_type] => utility [patent_app_number] => 14/088600 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088600 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088600
Global weak pattern history table filtering Nov 24, 2013 Issued
Array ( [id] => 9563773 [patent_doc_number] => 20140181486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'BRANCH PREDICTION TABLE INSTALL SOURCE TRACKING' [patent_app_type] => utility [patent_app_number] => 14/088504 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5101 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088504
Branch prediction table install source tracking Nov 24, 2013 Issued
Array ( [id] => 10517641 [patent_doc_number] => 09244688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Branch target buffer preload table' [patent_app_type] => utility [patent_app_number] => 14/088976 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6019 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14088976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/088976
Branch target buffer preload table Nov 24, 2013 Issued
Array ( [id] => 9332547 [patent_doc_number] => 20140059329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'ALLOCATION OF COUNTERS FROM A POOL OF COUNTERS TO TRACK MAPPINGS OF LOGICAL REGISTERS TO PHYSICAL REGISTERS FOR MAPPER BASED INSTRUCTION EXECUTIONS' [patent_app_type] => utility [patent_app_number] => 14/065795 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9625 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14065795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/065795
Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions Oct 28, 2013 Issued
Menu