Search

Melvin C. Marcelo

Examiner (ID: 7963, Phone: (571)272-3125 , Office: P/2463 )

Most Active Art Unit
2463
Art Unit(s)
2616, 2603, 2663, 2607, 2416, 2739, 2712, 2463, 2733, 2662
Total Applications
2145
Issued Applications
1788
Pending Applications
206
Abandoned Applications
176

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9919151 [patent_doc_number] => 20150074356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'PROCESSOR WITH MEMORY-EMBEDDED PIPELINE FOR TABLE-DRIVEN COMPUTATION' [patent_app_type] => utility [patent_app_number] => 14/053978 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5351 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053978 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/053978
Processor with memory-embedded pipeline for table-driven computation Oct 14, 2013 Issued
Array ( [id] => 11860813 [patent_doc_number] => 09740496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Processor with memory-embedded pipeline for table-driven computation' [patent_app_type] => utility [patent_app_number] => 14/019763 [patent_app_country] => US [patent_app_date] => 2013-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5316 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14019763 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/019763
Processor with memory-embedded pipeline for table-driven computation Sep 5, 2013 Issued
Array ( [id] => 10623367 [patent_doc_number] => 09342309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Extensible execution unit interface architecture with multiple decode logic and multiple execution units' [patent_app_type] => utility [patent_app_number] => 13/793443 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11103 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793443 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793443
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Mar 10, 2013 Issued
Array ( [id] => 9193399 [patent_doc_number] => 20130332714 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'FAST INDEX TREE FOR ACCELERATED BRANCH PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/784880 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10985 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784880 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784880
Fast index tree for accelerated branch prediction Mar 4, 2013 Issued
Array ( [id] => 9006130 [patent_doc_number] => 20130227255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'RECONFIGURABLE PROCESSOR, CODE CONVERSION APPARATUS THEREOF, AND CODE CONVERSION METHOD' [patent_app_type] => utility [patent_app_number] => 13/779961 [patent_app_country] => US [patent_app_date] => 2013-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4736 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13779961 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/779961
RECONFIGURABLE PROCESSOR, CODE CONVERSION APPARATUS THEREOF, AND CODE CONVERSION METHOD Feb 27, 2013 Abandoned
Array ( [id] => 10609839 [patent_doc_number] => 09329870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Extensible execution unit interface architecture with multiple decode logic and multiple execution units' [patent_app_type] => utility [patent_app_number] => 13/766508 [patent_app_country] => US [patent_app_date] => 2013-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 11065 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13766508 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/766508
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Feb 12, 2013 Issued
Array ( [id] => 11193229 [patent_doc_number] => 09424045 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit' [patent_app_type] => utility [patent_app_number] => 13/752621 [patent_app_country] => US [patent_app_date] => 2013-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752621 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752621
Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit Jan 28, 2013 Issued
Array ( [id] => 10948542 [patent_doc_number] => 20140351563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'ADVANCED PROCESSOR ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/365617 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 16065 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14365617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/365617
ADVANCED PROCESSOR ARCHITECTURE Dec 16, 2012 Abandoned
Array ( [id] => 11786546 [patent_doc_number] => 09395981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Multi-addressable register files and format conversions associated therewith' [patent_app_type] => utility [patent_app_number] => 13/716998 [patent_app_country] => US [patent_app_date] => 2012-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17206 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13716998 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/716998
Multi-addressable register files and format conversions associated therewith Dec 16, 2012 Issued
Array ( [id] => 9540090 [patent_doc_number] => 20140164738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION' [patent_app_type] => utility [patent_app_number] => 13/708544 [patent_app_country] => US [patent_app_date] => 2012-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5711 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13708544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/708544
INSTRUCTION CATEGORIZATION FOR RUNAHEAD OPERATION Dec 6, 2012 Abandoned
Array ( [id] => 10956230 [patent_doc_number] => 20140359252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/364643 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4315 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364643 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364643
Shared resource digital signal processors Nov 27, 2012 Issued
Array ( [id] => 10969695 [patent_doc_number] => 20140372728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-18 [patent_title] => 'VECTOR EXECUTION UNIT FOR DIGITAL SIGNAL PROCESSOR' [patent_app_type] => utility [patent_app_number] => 14/364651 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4491 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364651 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364651
VECTOR EXECUTION UNIT FOR DIGITAL SIGNAL PROCESSOR Nov 27, 2012 Abandoned
Array ( [id] => 10941528 [patent_doc_number] => 20140344549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/364629 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6255 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364629
DIGITAL SIGNAL PROCESSOR AND BASEBAND COMMUNICATION DEVICE Nov 27, 2012 Abandoned
Array ( [id] => 10524396 [patent_doc_number] => 09250911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-02 [patent_title] => 'Major branch instructions with transactional memory' [patent_app_type] => utility [patent_app_number] => 13/678217 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15025 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 568 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13678217 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/678217
Major branch instructions with transactional memory Nov 14, 2012 Issued
Array ( [id] => 10562461 [patent_doc_number] => 09286138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Major branch instructions' [patent_app_type] => utility [patent_app_number] => 13/678185 [patent_app_country] => US [patent_app_date] => 2012-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 15011 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13678185 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/678185
Major branch instructions Nov 14, 2012 Issued
Array ( [id] => 8722880 [patent_doc_number] => 20130074097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'ENDPOINT-BASED PARALLEL DATA PROCESSING WITH NON-BLOCKING COLLECTIVE INSTRUCTIONS IN A PARALLEL ACTIVE MESSAGING INTERFACE OF A PARALLEL COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/671762 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 18492 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671762 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671762
Endpoint-based parallel data processing with non-blocking collective instructions in a parallel active messaging interface of a parallel computer Nov 7, 2012 Issued
Array ( [id] => 9465379 [patent_doc_number] => 20140129806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'LOAD/STORE PICKER' [patent_app_type] => utility [patent_app_number] => 13/672224 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672224 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672224
LOAD/STORE PICKER Nov 7, 2012 Abandoned
Array ( [id] => 9465378 [patent_doc_number] => 20140129805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-08 [patent_title] => 'EXECUTION PIPELINE POWER REDUCTION' [patent_app_type] => utility [patent_app_number] => 13/672585 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672585 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672585
EXECUTION PIPELINE POWER REDUCTION Nov 7, 2012 Abandoned
Array ( [id] => 9878928 [patent_doc_number] => 08966224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Performing a deterministic reduction operation in a parallel computer' [patent_app_type] => utility [patent_app_number] => 13/665985 [patent_app_country] => US [patent_app_date] => 2012-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10047 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13665985 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/665985
Performing a deterministic reduction operation in a parallel computer Oct 31, 2012 Issued
Array ( [id] => 11598655 [patent_doc_number] => 09645824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Branch target address cache using hashed fetch addresses' [patent_app_type] => utility [patent_app_number] => 13/664659 [patent_app_country] => US [patent_app_date] => 2012-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3233 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13664659 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/664659
Branch target address cache using hashed fetch addresses Oct 30, 2012 Issued
Menu