Search

Melvin Feifer

Examiner (ID: 5713)

Most Active Art Unit
2902
Art Unit(s)
2902, 2912, 2900
Total Applications
2696
Issued Applications
2667
Pending Applications
0
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18884929 [patent_doc_number] => 20240008298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME [patent_app_type] => utility [patent_app_number] => 18/451538 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451538 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/451538
LIGHT EMITTING DIODE DISPLAY WITH REDUNDANCY SCHEME Aug 16, 2023 Pending
Array ( [id] => 18848810 [patent_doc_number] => 20230411214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 18/363247 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18363247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/363247
JET ABLATION DIE SINGULATION SYSTEMS AND RELATED METHODS Jul 31, 2023 Pending
Array ( [id] => 18789487 [patent_doc_number] => 20230378159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/362960 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362960 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362960
INTEGRATED CIRCUIT DEVICE AND METHOD Jul 31, 2023 Pending
Array ( [id] => 19524064 [patent_doc_number] => 12125804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-22 [patent_title] => Semiconductor package and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/362989 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 46 [patent_no_of_words] => 13306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18362989 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/362989
Semiconductor package and manufacturing method thereof Jul 31, 2023 Issued
Array ( [id] => 19567803 [patent_doc_number] => 12142582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Organic interposer including a dual-layer inductor structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/360883 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 10193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360883 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360883
ORGANIC INTERPOSER INCLUDING A DUAL-LAYER INDUCTOR STRUCTURE AND METHODS OF FORMING THE SAME Jul 27, 2023 Pending
Array ( [id] => 18906044 [patent_doc_number] => 20240021529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => PACKAGE STRUCTURE WITH UNDERFILL [patent_app_type] => utility [patent_app_number] => 18/359924 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359924
PACKAGE STRUCTURE WITH UNDERFILL Jul 26, 2023 Pending
Array ( [id] => 18774308 [patent_doc_number] => 20230369139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => METHOD OF TESTING SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/359887 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359887 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/359887
METHOD OF TESTING SEMICONDUCTOR PACKAGE Jul 26, 2023 Pending
Array ( [id] => 18810349 [patent_doc_number] => 20230384684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 18/358904 [patent_app_country] => US [patent_app_date] => 2023-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18358904 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/358904
METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR Jul 24, 2023 Pending
Array ( [id] => 18757532 [patent_doc_number] => 20230360995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => METHOD OF FABRICATING PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/356227 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356227 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356227
METHOD OF FABRICATING PACKAGE STRUCTURE Jul 20, 2023 Pending
Array ( [id] => 19567800 [patent_doc_number] => 12142579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-12 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/354633 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 8771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18354633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/354633
PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF Jul 17, 2023 Pending
Array ( [id] => 18789320 [patent_doc_number] => 20230377973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/223035 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223035 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/223035
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND WAFER-ATTACHED STRUCTURE Jul 17, 2023 Pending
Array ( [id] => 19370510 [patent_doc_number] => 12062604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Semiconductor structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/350730 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 37 [patent_no_of_words] => 12021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350730 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350730
Semiconductor structure and manufacturing method thereof Jul 10, 2023 Issued
Array ( [id] => 19553898 [patent_doc_number] => 12137621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Intercalated metal/dielectric structure for nonvolatile memory devices [patent_app_type] => utility [patent_app_number] => 18/336088 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 6504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/336088
Intercalated metal/dielectric structure for nonvolatile memory devices Jun 15, 2023 Issued
Array ( [id] => 19492557 [patent_doc_number] => 12111261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Integrated photodetector with direct binning pixel [patent_app_type] => utility [patent_app_number] => 18/330295 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 41 [patent_no_of_words] => 17450 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330295 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330295
Integrated photodetector with direct binning pixel Jun 5, 2023 Issued
Array ( [id] => 18696440 [patent_doc_number] => 20230326879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/328913 [patent_app_country] => US [patent_app_date] => 2023-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328913 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328913
PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME Jun 4, 2023 Pending
Array ( [id] => 19399747 [patent_doc_number] => 12074135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor device and method of controlling warpage during LAB [patent_app_type] => utility [patent_app_number] => 18/315991 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3039 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315991 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315991
Semiconductor device and method of controlling warpage during LAB May 10, 2023 Issued
Array ( [id] => 18600169 [patent_doc_number] => 20230274970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/312655 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11304 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312655
WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE May 4, 2023 Pending
Array ( [id] => 19414748 [patent_doc_number] => 12080585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Wet alignment method for micro-semiconductor chip and display transfer structure [patent_app_type] => utility [patent_app_number] => 18/312641 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 47 [patent_no_of_words] => 11303 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312641
Wet alignment method for micro-semiconductor chip and display transfer structure May 4, 2023 Issued
Array ( [id] => 19507836 [patent_doc_number] => 12119266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Semiconductor arrangement and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/142142 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6014 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142142
Semiconductor arrangement and method of manufacture May 1, 2023 Issued
Array ( [id] => 19444560 [patent_doc_number] => 12094851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Particle capture using transfer stamp [patent_app_type] => utility [patent_app_number] => 18/132199 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 8802 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132199
Particle capture using transfer stamp Apr 6, 2023 Issued
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