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Melvin Feifer

Examiner (ID: 9158)

Most Active Art Unit
2902
Art Unit(s)
2902, 2900, 2912
Total Applications
2696
Issued Applications
2667
Pending Applications
0
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1485052 [patent_doc_number] => 06453403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'System and method for memory management using contiguous fixed-size blocks' [patent_app_type] => B1 [patent_app_number] => 09/574967 [patent_app_country] => US [patent_app_date] => 2000-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6036 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453403.pdf [firstpage_image] =>[orig_patent_app_number] => 09574967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/574967
System and method for memory management using contiguous fixed-size blocks May 18, 2000 Issued
Array ( [id] => 1501526 [patent_doc_number] => 06405281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Input/output methods for associative processor' [patent_app_type] => B1 [patent_app_number] => 09/572583 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11953 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405281.pdf [firstpage_image] =>[orig_patent_app_number] => 09572583 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572583
Input/output methods for associative processor May 16, 2000 Issued
Array ( [id] => 1509003 [patent_doc_number] => 06467020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Combined associate processor and memory architecture' [patent_app_type] => B1 [patent_app_number] => 09/572582 [patent_app_country] => US [patent_app_date] => 2000-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7734 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467020.pdf [firstpage_image] =>[orig_patent_app_number] => 09572582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/572582
Combined associate processor and memory architecture May 16, 2000 Issued
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