Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3892174
[patent_doc_number] => 05777346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Metal oxide semiconductor controlled thyristor with an on-field effect transistor in a trench'
[patent_app_type] => 1
[patent_app_number] => 8/586613
[patent_app_country] => US
[patent_app_date] => 1996-01-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/586613 | Metal oxide semiconductor controlled thyristor with an on-field effect transistor in a trench | Jan 15, 1996 | Issued |
Array
(
[id] => 3943610
[patent_doc_number] => 05872398
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Reduced stress LOC assembly including cantilevered leads'
[patent_app_type] => 1
[patent_app_number] => 8/584738
[patent_app_country] => US
[patent_app_date] => 1996-01-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/584738 | Reduced stress LOC assembly including cantilevered leads | Jan 10, 1996 | Issued |
Array
(
[id] => 3668784
[patent_doc_number] => 05668394
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'Prevention of fluorine-induced gate oxide degradation in WSi polycide structure'
[patent_app_type] => 1
[patent_app_number] => 8/582599
[patent_app_country] => US
[patent_app_date] => 1996-01-03
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 582599
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Array
(
[id] => 3933331
[patent_doc_number] => 05877549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'UFBGA package equipped with interface assembly including a photosoluble layer'
[patent_app_type] => 1
[patent_app_number] => 8/581956
[patent_app_country] => US
[patent_app_date] => 1996-01-02
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 581956
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/581956 | UFBGA package equipped with interface assembly including a photosoluble layer | Jan 1, 1996 | Issued |
08/581781 | RESIN-SEALED TYPE SEMICONDUCTOR DEVICE | Dec 28, 1995 | Abandoned |
08/578913 | SEMICONDUCTOR INTERCONNECTION DEVICE AND MANUFACTURING METHOD | Dec 26, 1995 | Abandoned |
Array
(
[id] => 3831070
[patent_doc_number] => 05783855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-21
[patent_title] => 'Lateral transistor'
[patent_app_type] => 1
[patent_app_number] => 8/577373
[patent_app_country] => US
[patent_app_date] => 1995-12-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 577373
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Array
(
[id] => 3666767
[patent_doc_number] => 05625223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-29
[patent_title] => 'Surface mounting type diode'
[patent_app_type] => 1
[patent_app_number] => 8/577511
[patent_app_country] => US
[patent_app_date] => 1995-12-22
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[firstpage_image] =>[orig_patent_app_number] => 577511
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Array
(
[id] => 3653308
[patent_doc_number] => 05640043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-17
[patent_title] => 'High voltage silicon diode with optimum placement of silicon-germanium layers'
[patent_app_type] => 1
[patent_app_number] => 8/580071
[patent_app_country] => US
[patent_app_date] => 1995-12-20
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[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/640/05640043.pdf
[firstpage_image] =>[orig_patent_app_number] => 580071
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580071 | High voltage silicon diode with optimum placement of silicon-germanium layers | Dec 19, 1995 | Issued |
Array
(
[id] => 3882758
[patent_doc_number] => 05747867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Integrated circuit structure with interconnect formed along walls of silicon island'
[patent_app_type] => 1
[patent_app_number] => 8/573359
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2743
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/747/05747867.pdf
[firstpage_image] =>[orig_patent_app_number] => 573359
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573359 | Integrated circuit structure with interconnect formed along walls of silicon island | Dec 14, 1995 | Issued |
Array
(
[id] => 3766429
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Vertical semiconductor device and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 8/569449
[patent_app_country] => US
[patent_app_date] => 1995-12-08
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[pdf_file] => patents/05/844/05844273.pdf
[firstpage_image] =>[orig_patent_app_number] => 569449
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/569449 | Vertical semiconductor device and method of manufacturing the same | Dec 7, 1995 | Issued |
Array
(
[id] => 3520244
[patent_doc_number] => 05576575
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Semiconductor conversion device'
[patent_app_type] => 1
[patent_app_number] => 8/567796
[patent_app_country] => US
[patent_app_date] => 1995-12-06
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 567796
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/567796 | Semiconductor conversion device | Dec 5, 1995 | Issued |
Array
(
[id] => 4070281
[patent_doc_number] => 05866952
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate'
[patent_app_type] => 1
[patent_app_number] => 8/565269
[patent_app_country] => US
[patent_app_date] => 1995-11-30
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[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/866/05866952.pdf
[firstpage_image] =>[orig_patent_app_number] => 565269
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/565269 | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate | Nov 29, 1995 | Issued |
08/566161 | PRODUCT RESULTING FROM SELECTIVE DEPOSITION OF POLYSILICON OVER SINGLE CRYSTAL SILICON SUBSTRATE | Nov 29, 1995 | Abandoned |
08/561523 | BREAKOVER-TRIGGERED DIPOLE COMPONENT HAVING A CONTROLLED SENSITIVITY | Nov 20, 1995 | Abandoned |
Array
(
[id] => 3710690
[patent_doc_number] => 05654576
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Post-titanium nitride mask ROM programming method and device manufactured thereby'
[patent_app_type] => 1
[patent_app_number] => 8/559324
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 559324
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/559324 | Post-titanium nitride mask ROM programming method and device manufactured thereby | Nov 15, 1995 | Issued |
Array
(
[id] => 3530843
[patent_doc_number] => 05541451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions'
[patent_app_type] => 1
[patent_app_number] => 8/554105
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[firstpage_image] =>[orig_patent_app_number] => 554105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/554105 | Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions | Nov 5, 1995 | Issued |
Array
(
[id] => 3729983
[patent_doc_number] => 05701032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'Integrated circuit package'
[patent_app_type] => 1
[patent_app_number] => 8/552359
[patent_app_country] => US
[patent_app_date] => 1995-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/05/701/05701032.pdf
[firstpage_image] =>[orig_patent_app_number] => 552359
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/552359 | Integrated circuit package | Nov 1, 1995 | Issued |
08/550401 | SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION | Oct 29, 1995 | Abandoned |
Array
(
[id] => 3624657
[patent_doc_number] => 05641988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Multi-layered, integrated circuit package having reduced parasitic noise characteristics'
[patent_app_type] => 1
[patent_app_number] => 8/549985
[patent_app_country] => US
[patent_app_date] => 1995-10-30
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[pdf_file] => patents/05/641/05641988.pdf
[firstpage_image] =>[orig_patent_app_number] => 549985
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/549985 | Multi-layered, integrated circuit package having reduced parasitic noise characteristics | Oct 29, 1995 | Issued |