Search

Meng Li

Examiner (ID: 14750, Phone: (571)272-8729 , Office: P/2437 )

Most Active Art Unit
2437
Art Unit(s)
2437, 2496
Total Applications
660
Issued Applications
537
Pending Applications
64
Abandoned Applications
67

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18712872 [patent_doc_number] => 20230335505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => MANUFACTURING PROCESS STEPS OF A SEMICONDUCTOR DEVICE PACKAGE [patent_app_type] => utility [patent_app_number] => 18/212162 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18212162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/212162
Semiconductor device package structure comprising package unit including adhesive layer Jun 19, 2023 Issued
Array ( [id] => 19428164 [patent_doc_number] => 12087597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Semiconductor structure comprising various via structures [patent_app_type] => utility [patent_app_number] => 18/331961 [patent_app_country] => US [patent_app_date] => 2023-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331961 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331961
Semiconductor structure comprising various via structures Jun 8, 2023 Issued
Array ( [id] => 18680006 [patent_doc_number] => 20230317664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => INTEGRATED CIRCUIT PACKAGES HAVING ADHESION LAYERS FOR THROUGH VIAS [patent_app_type] => utility [patent_app_number] => 18/330616 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11423 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330616 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330616
Integrated circuit packages having adhesion layers for through vias Jun 6, 2023 Issued
Array ( [id] => 19639696 [patent_doc_number] => 12170313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-17 [patent_title] => Heterojunction bipolar transistor with buried trap rich isolation region [patent_app_type] => utility [patent_app_number] => 18/324637 [patent_app_country] => US [patent_app_date] => 2023-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18324637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/324637
Heterojunction bipolar transistor with buried trap rich isolation region May 25, 2023 Issued
Array ( [id] => 19589693 [patent_doc_number] => 20240387250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SELF-ALIGNED INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/199568 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18199568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/199568
SELF-ALIGNED INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF May 18, 2023 Pending
Array ( [id] => 18774335 [patent_doc_number] => 20230369166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 18/316376 [patent_app_country] => US [patent_app_date] => 2023-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18316376 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/316376
POWER SEMICONDUCTOR MODULE ARRANGEMENT AND METHOD FOR PRODUCING THE SAME May 11, 2023 Pending
Array ( [id] => 19575188 [patent_doc_number] => 20240379480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Semiconductor Device and Method of Making a Dual-Side Molded System-in-Package with Fine-Pitched Interconnects [patent_app_type] => utility [patent_app_number] => 18/315964 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315964
Semiconductor Device and Method of Making a Dual-Side Molded System-in-Package with Fine-Pitched Interconnects May 10, 2023 Issued
Array ( [id] => 18789424 [patent_doc_number] => 20230378088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => APPARATUS AND METHOD FOR SELECTIVELY FORMING A SHIELDING LAYER ON A SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/315490 [patent_app_country] => US [patent_app_date] => 2023-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315490 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315490
APPARATUS AND METHOD FOR SELECTIVELY FORMING A SHIELDING LAYER ON A SEMICONDUCTOR PACKAGE May 9, 2023 Pending
Array ( [id] => 18848900 [patent_doc_number] => 20230411304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/313316 [patent_app_country] => US [patent_app_date] => 2023-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313316 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/313316
Semiconductor device comprising different shielding layers to provide reduced electromagnetic interference and method for making the same May 5, 2023 Issued
Array ( [id] => 18601871 [patent_doc_number] => 20230276677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => DISPLAY PANEL HAVING AN ARRANGEMENT BY UNIT PIXEL PAIRS [patent_app_type] => utility [patent_app_number] => 18/312937 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312937
Display panel having an arrangement by unit pixel pairs May 4, 2023 Issued
Array ( [id] => 18600149 [patent_doc_number] => 20230274950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR DIE PACKAGE [patent_app_type] => utility [patent_app_number] => 18/311980 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8634 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18311980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/311980
Method for forming semiconductor die package with ring structure comprising recessed parts May 3, 2023 Issued
Array ( [id] => 18812700 [patent_doc_number] => 20230387037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Shielding circuits and semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/143056 [patent_app_country] => US [patent_app_date] => 2023-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143056 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143056
Shielding circuits and semiconductor devices May 2, 2023 Pending
Array ( [id] => 18812613 [patent_doc_number] => 20230386950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => 3D FAN-OUT PACKAGING STRUCTURE OF INTERCONNECTION SYSTEM WITH ULTRA-HIGH DENSITY AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/142416 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18142416 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/142416
3D FAN-OUT PACKAGING STRUCTURE OF INTERCONNECTION SYSTEM WITH ULTRA-HIGH DENSITY AND METHOD FOR MANUFACTURING THE SAME May 1, 2023 Pending
Array ( [id] => 20528369 [patent_doc_number] => 12546801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Wafer structure comprising multiple chips and dummy connectors including bonding and probing segments [patent_app_type] => utility [patent_app_number] => 18/310541 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310541
Wafer structure comprising multiple chips and dummy connectors including bonding and probing segments May 1, 2023 Issued
Array ( [id] => 18586097 [patent_doc_number] => 20230268362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METAL MIRROR BASED MULTISPECTRAL FILTER ARRAY [patent_app_type] => utility [patent_app_number] => 18/310769 [patent_app_country] => US [patent_app_date] => 2023-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18310769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/310769
Metal mirror based multispectral filter array of optical sensor device May 1, 2023 Issued
Array ( [id] => 19546655 [patent_doc_number] => 20240363691 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => WIDE BANDGAP MATERIAL IN DRIFT WELL OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/309504 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8127 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309504
WIDE BANDGAP MATERIAL IN DRIFT WELL OF SEMICONDUCTOR DEVICE Apr 27, 2023 Pending
Array ( [id] => 18586165 [patent_doc_number] => 20230268430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING DIFFERENT NITRIDE REGIONS AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 18/307099 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307099 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307099
Semiconductor device including different nitride regions improving characteristics of the semiconductor device Apr 25, 2023 Issued
Array ( [id] => 18743455 [patent_doc_number] => 20230352443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => METHODS OF IMPROVING WIRE BONDING OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/139209 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139209 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/139209
METHODS OF IMPROVING WIRE BONDING OPERATIONS Apr 24, 2023 Pending
Array ( [id] => 18570530 [patent_doc_number] => 20230260867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => HEAT DISPERSION LAYERS FOR DOUBLE SIDED INTERCONNECT [patent_app_type] => utility [patent_app_number] => 18/304563 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9130 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304563
Heat dispersion layers for double sided interconnect Apr 20, 2023 Issued
Array ( [id] => 19029992 [patent_doc_number] => 11929358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Display backplate and method for manufacturing same, display panel and method for manufacturing same, and display device [patent_app_type] => utility [patent_app_number] => 18/137857 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 57 [patent_no_of_words] => 12281 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137857 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137857
Display backplate and method for manufacturing same, display panel and method for manufacturing same, and display device Apr 20, 2023 Issued
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