Search

Metasebia T. Retebo

Examiner (ID: 16326, Phone: (571)272-9299 , Office: P/2842 )

Most Active Art Unit
2842
Art Unit(s)
2836, 2842
Total Applications
765
Issued Applications
630
Pending Applications
89
Abandoned Applications
68

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20837346 [patent_doc_number] => 20260196863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-07-09 [patent_title] => NETWORK SWITCH PORT SHED [patent_app_type] => utility [patent_app_number] => 19/538146 [patent_app_country] => US [patent_app_date] => 2026-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19538146 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/538146
NETWORK SWITCH PORT SHED Feb 11, 2026 Pending
Array ( [id] => 20284652 [patent_doc_number] => 20250309894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => FUSE STRUCTURE [patent_app_type] => utility [patent_app_number] => 19/237286 [patent_app_country] => US [patent_app_date] => 2025-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19237286 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/237286
FUSE STRUCTURE Jun 12, 2025 Pending
Array ( [id] => 20236370 [patent_doc_number] => 20250293689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => SLEW RATE CONTROLLED OUTPUT BUFFER CIRCUIT AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 19/227501 [patent_app_country] => US [patent_app_date] => 2025-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19227501 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/227501
SLEW RATE CONTROLLED OUTPUT BUFFER CIRCUIT AND SEMICONDUCTOR DEVICE Jun 3, 2025 Pending
Array ( [id] => 20154003 [patent_doc_number] => 20250253841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-07 [patent_title] => SEMICONDUCTOR SWITCHING MODULE WITH INSULATED GATE BIPOLAR TRANSISTOR AND UNIPOLAR SWITCHING DEVICE [patent_app_type] => utility [patent_app_number] => 19/187273 [patent_app_country] => US [patent_app_date] => 2025-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19187273 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/187273
SEMICONDUCTOR SWITCHING MODULE WITH INSULATED GATE BIPOLAR TRANSISTOR AND UNIPOLAR SWITCHING DEVICE Apr 22, 2025 Pending
Array ( [id] => 20298336 [patent_doc_number] => 20250323579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => INTERFACE CIRCUIT USING MIRRORED CURRENT FEEDBACK TO REDUCE INPUT IMPEDANCE [patent_app_type] => utility [patent_app_number] => 19/048681 [patent_app_country] => US [patent_app_date] => 2025-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19048681 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/048681
INTERFACE CIRCUIT USING MIRRORED CURRENT FEEDBACK TO REDUCE INPUT IMPEDANCE Feb 6, 2025 Pending
Array ( [id] => 20325311 [patent_doc_number] => 20250337399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => BUFFER AND INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 19/023094 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023094 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023094
BUFFER AND INTEGRATED CIRCUIT Jan 14, 2025 Pending
Array ( [id] => 20448962 [patent_doc_number] => 20260005688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => ISOLATED GATE DRIVE CIRCUIT AND DRIVER [patent_app_type] => utility [patent_app_number] => 19/019041 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19019041 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/019041
ISOLATED GATE DRIVE CIRCUIT AND DRIVER Jan 12, 2025 Pending
Array ( [id] => 20926091 [patent_doc_number] => 12721181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Transient stabilized SOI FETs [patent_app_type] => utility [patent_app_number] => 19/018452 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 7975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018452 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018452
Transient Stabilized SOI FETs Jan 12, 2025 Pending
Array ( [id] => 20630889 [patent_doc_number] => 20260095178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => ADAPTIVE POWER SWITCH [patent_app_type] => utility [patent_app_number] => 19/014884 [patent_app_country] => US [patent_app_date] => 2025-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19014884 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/014884
ADAPTIVE POWER SWITCH Jan 8, 2025 Pending
Array ( [id] => 20096888 [patent_doc_number] => 20250226824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => LOAD SWITCH CIRCUIT AND CONTROLLING CIRCUIT OF THE SAME [patent_app_type] => utility [patent_app_number] => 19/009184 [patent_app_country] => US [patent_app_date] => 2025-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19009184 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/009184
LOAD SWITCH CIRCUIT AND CONTROLLING CIRCUIT OF THE SAME Jan 2, 2025 Pending
Array ( [id] => 19994538 [patent_doc_number] => 20250132760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => SIGNAL PROCESSING DEVICE AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/999623 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1044 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18999623 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/999623
SIGNAL PROCESSING DEVICE AND CONTROL METHOD Dec 22, 2024 Pending
Array ( [id] => 20089688 [patent_doc_number] => 20250219624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SLEW RATE PROTECTION CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/999022 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18999022 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/999022
SLEW RATE PROTECTION CIRCUIT Dec 22, 2024 Pending
Array ( [id] => 20096883 [patent_doc_number] => 20250226819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => I2C INTERFACE CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/987504 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987504
I2C INTERFACE CIRCUIT, CORRESPONDING ELECTRONIC DEVICE AND METHOD OF OPERATION Dec 18, 2024 Pending
Array ( [id] => 20556785 [patent_doc_number] => 20260056569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-26 [patent_title] => VOLTAGE REFERENCE CIRCUIT WITH OFFSET TRIMMING USING FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/983422 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18983422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/983422
VOLTAGE REFERENCE CIRCUIT WITH OFFSET TRIMMING USING FIELD-EFFECT TRANSISTORS Dec 16, 2024 Pending
Array ( [id] => 19851449 [patent_doc_number] => 20250096800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => MULTIPLEXING CIRCUIT, OUTPUT STAGE, AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/970786 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970786 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970786
MULTIPLEXING CIRCUIT, OUTPUT STAGE, AND SEMICONDUCTOR DEVICE Dec 4, 2024 Pending
Array ( [id] => 20806480 [patent_doc_number] => 12671395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Process voltage temperature compensated current-starved inverter ring oscillator [patent_app_type] => utility [patent_app_number] => 18/957115 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1169 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/957115
Process voltage temperature compensated current-starved inverter ring oscillator Nov 21, 2024 Issued
Array ( [id] => 19836400 [patent_doc_number] => 20250088186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SWITCHING TRANDUCER DRIVER [patent_app_type] => utility [patent_app_number] => 18/948973 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948973
SWITCHING TRANDUCER DRIVER Nov 14, 2024 Pending
Array ( [id] => 19804842 [patent_doc_number] => 20250070767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SIGNAL TRANSMISSION DEVICE CAPABLE OF SHORTENING TURN-OFF TIME OF CONTROLLED SOURCE IN ELECTROMAGNETIC METHOD [patent_app_type] => utility [patent_app_number] => 18/945463 [patent_app_country] => US [patent_app_date] => 2024-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/945463
Signal transmission device capable of shortening turn-off time of controlled source in electromagnetic method Nov 11, 2024 Issued
Array ( [id] => 20929891 [patent_doc_number] => 12724061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-09-01 [patent_title] => GaN reliability built-in self test (BIST) apparatus and method for qualifying dynamic on-state resistance degradation [patent_app_type] => utility [patent_app_number] => 18/936841 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1177 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18936841 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/936841
GAN RELIABILITY BUILT-IN SELF TEST (BIST) APPARATUS AND METHOD FOR QUALIFYING DYNAMIC ON-STATE RESISTANCE DEGRADATION Nov 3, 2024 Pending
Array ( [id] => 19774025 [patent_doc_number] => 20250055451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => UNDER VOLTAGE LOCK-OUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/928390 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928390 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928390
UNDER VOLTAGE LOCK-OUT CIRCUIT Oct 27, 2024 Pending
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