
Metasebia T. Retebo
Examiner (ID: 767, Phone: (571)272-9299 , Office: P/2842 )
| Most Active Art Unit | 2842 |
| Art Unit(s) | 2842, 2836 |
| Total Applications | 744 |
| Issued Applications | 620 |
| Pending Applications | 82 |
| Abandoned Applications | 66 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13086293
[patent_doc_number] => 10063222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-08-28
[patent_title] => Dynamic control of edge shift for duty cycle correction
[patent_app_type] => utility
[patent_app_number] => 15/714438
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 6281
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714438
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714438 | Dynamic control of edge shift for duty cycle correction | Sep 24, 2017 | Issued |
Array
(
[id] => 14111883
[patent_doc_number] => 20190097617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-28
[patent_title] => CORRECTING DUTY CYCLE AND COMPENSATING FOR ACTIVE CLOCK EDGE SHIFT
[patent_app_type] => utility
[patent_app_number] => 15/714012
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16399
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714012
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714012 | Correcting duty cycle and compensating for active clock edge shift | Sep 24, 2017 | Issued |
Array
(
[id] => 15986205
[patent_doc_number] => 10673445
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Time-to-digital converter in phase-locked loop
[patent_app_type] => utility
[patent_app_number] => 15/713410
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6444
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713410
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/713410 | Time-to-digital converter in phase-locked loop | Sep 21, 2017 | Issued |
Array
(
[id] => 16294196
[patent_doc_number] => 10771054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-08
[patent_title] => Control circuit for solid state power controller
[patent_app_type] => utility
[patent_app_number] => 15/712180
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 7907
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 372
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712180
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/712180 | Control circuit for solid state power controller | Sep 21, 2017 | Issued |
Array
(
[id] => 16607557
[patent_doc_number] => 10908558
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Circuit device, physical quantity measurement device, electronic apparatus, and vehicle
[patent_app_type] => utility
[patent_app_number] => 15/712879
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 21
[patent_no_of_words] => 20275
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712879
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/712879 | Circuit device, physical quantity measurement device, electronic apparatus, and vehicle | Sep 21, 2017 | Issued |
Array
(
[id] => 14080945
[patent_doc_number] => 20190089360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-21
[patent_title] => Variable Delay
[patent_app_type] => utility
[patent_app_number] => 15/711924
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12896
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711924
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/711924 | Variable delay | Sep 20, 2017 | Issued |
Array
(
[id] => 14080941
[patent_doc_number] => 20190089358
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-03-21
[patent_title] => Delay-Locked Loop (DLL) with Differential Delay Lines
[patent_app_type] => utility
[patent_app_number] => 15/711708
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12333
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15711708
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/711708 | Delay-locked loop (DLL) with differential delay lines | Sep 20, 2017 | Issued |
Array
(
[id] => 16889686
[patent_doc_number] => 20210175883
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-10
[patent_title] => DEVICE AND METHOD FOR CONTROLLING SWITCHING
[patent_app_type] => utility
[patent_app_number] => 16/325093
[patent_app_country] => US
[patent_app_date] => 2017-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6232
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16325093
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/325093 | Device and method for controlling switching | Sep 18, 2017 | Issued |
Array
(
[id] => 14604947
[patent_doc_number] => 10355673
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-16
[patent_title] => Semiconductor device and electronic device
[patent_app_type] => utility
[patent_app_number] => 15/706984
[patent_app_country] => US
[patent_app_date] => 2017-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 27
[patent_no_of_words] => 23919
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706984
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/706984 | Semiconductor device and electronic device | Sep 17, 2017 | Issued |
Array
(
[id] => 15582081
[patent_doc_number] => 10581441
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-03
[patent_title] => Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power
[patent_app_type] => utility
[patent_app_number] => 15/706449
[patent_app_country] => US
[patent_app_date] => 2017-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3999
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706449
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/706449 | Apparatus and method for generating clock signal with low jitter and constant frequency while consuming low power | Sep 14, 2017 | Issued |
Array
(
[id] => 14708429
[patent_doc_number] => 10381981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-13
[patent_title] => Degeneration for a wideband voltage-controlled oscillator
[patent_app_type] => utility
[patent_app_number] => 15/706034
[patent_app_country] => US
[patent_app_date] => 2017-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5350
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15706034
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/706034 | Degeneration for a wideband voltage-controlled oscillator | Sep 14, 2017 | Issued |
Array
(
[id] => 16339838
[patent_doc_number] => 10790810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-29
[patent_title] => Balancer for multiple field effect transistors arranged in a parallel configuration
[patent_app_type] => utility
[patent_app_number] => 15/705718
[patent_app_country] => US
[patent_app_date] => 2017-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6168
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15705718
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/705718 | Balancer for multiple field effect transistors arranged in a parallel configuration | Sep 14, 2017 | Issued |
Array
(
[id] => 13335997
[patent_doc_number] => 20180219537
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-02
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 15/704641
[patent_app_country] => US
[patent_app_date] => 2017-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6541
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704641
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/704641 | Electronic device | Sep 13, 2017 | Issued |
Array
(
[id] => 12264423
[patent_doc_number] => 20180083618
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-03-22
[patent_title] => 'SWITCH APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 15/701447
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11798
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701447
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/701447 | Switch apparatus | Sep 11, 2017 | Issued |
Array
(
[id] => 14986429
[patent_doc_number] => 10447139
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-15
[patent_title] => Load driving apparatus
[patent_app_type] => utility
[patent_app_number] => 15/701661
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 7187
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701661
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/701661 | Load driving apparatus | Sep 11, 2017 | Issued |
Array
(
[id] => 15704889
[patent_doc_number] => 10608637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-31
[patent_title] => Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison
[patent_app_type] => utility
[patent_app_number] => 15/698022
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4082
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698022
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698022 | Supply voltage compensation for an input/output driver circuit using clock signal frequency comparison | Sep 6, 2017 | Issued |
Array
(
[id] => 12718600
[patent_doc_number] => 20180131366
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-10
[patent_title] => RF Switch with Bypass Topology
[patent_app_type] => utility
[patent_app_number] => 15/698088
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15698088
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/698088 | RF Switch with Bypass Topology | Sep 6, 2017 | Abandoned |
Array
(
[id] => 12173496
[patent_doc_number] => 09891637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-02-13
[patent_title] => 'Method for powering a module incorporated within a system-on-a-chip and corresponding electronic device'
[patent_app_type] => utility
[patent_app_number] => 15/696459
[patent_app_country] => US
[patent_app_date] => 2017-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4919
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696459
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/696459 | Method for powering a module incorporated within a system-on-a-chip and corresponding electronic device | Sep 5, 2017 | Issued |
Array
(
[id] => 13964271
[patent_doc_number] => 20190058480
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-21
[patent_title] => INJECTION-LOCKED DIGITAL BANG-BANG PHASE-LOCKED LOOP WITH TIMING CALIBRATION
[patent_app_type] => utility
[patent_app_number] => 15/693257
[patent_app_country] => US
[patent_app_date] => 2017-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4882
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693257
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/693257 | Injection-locked digital bang-bang phase-locked loop with timing calibration | Aug 30, 2017 | Issued |
Array
(
[id] => 15062837
[patent_doc_number] => 10461735
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-10-29
[patent_title] => Electrical switching apparatus comprising an improved electrically interconnect device
[patent_app_type] => utility
[patent_app_number] => 15/687188
[patent_app_country] => US
[patent_app_date] => 2017-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3554
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687188
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/687188 | Electrical switching apparatus comprising an improved electrically interconnect device | Aug 24, 2017 | Issued |