Search

Mia M. Thomas

Examiner (ID: 12892, Phone: (571)270-1583 , Office: P/2669 )

Most Active Art Unit
2665
Art Unit(s)
2665, 2669, 2624
Total Applications
923
Issued Applications
772
Pending Applications
55
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1250212 [patent_doc_number] => 06675236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Field bus interface board' [patent_app_type] => B2 [patent_app_number] => 09/960934 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2451 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675236.pdf [firstpage_image] =>[orig_patent_app_number] => 09960934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960934
Field bus interface board Sep 24, 2001 Issued
Array ( [id] => 1138849 [patent_doc_number] => 06789143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Infiniband work and completion queue management via head and tail circular buffers with indirect work queue entries' [patent_app_type] => B2 [patent_app_number] => 09/961922 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 11665 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789143.pdf [firstpage_image] =>[orig_patent_app_number] => 09961922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961922
Infiniband work and completion queue management via head and tail circular buffers with indirect work queue entries Sep 23, 2001 Issued
Array ( [id] => 6413787 [patent_doc_number] => 20020038395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'USB interface-compatible computer peripheral unit' [patent_app_type] => new [patent_app_number] => 09/960681 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2452 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038395.pdf [firstpage_image] =>[orig_patent_app_number] => 09960681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960681
USB interface-compatible computer peripheral unit Sep 20, 2001 Issued
Array ( [id] => 7962309 [patent_doc_number] => 06681275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'Method and apparatus for dynamic coalescing' [patent_app_type] => B2 [patent_app_number] => 09/961108 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3931 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681275.pdf [firstpage_image] =>[orig_patent_app_number] => 09961108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961108
Method and apparatus for dynamic coalescing Sep 19, 2001 Issued
Array ( [id] => 6722347 [patent_doc_number] => 20030056037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Hardware chain pull' [patent_app_type] => new [patent_app_number] => 09/957106 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20030056037.pdf [firstpage_image] =>[orig_patent_app_number] => 09957106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957106
Hardware chain pull Sep 19, 2001 Issued
Array ( [id] => 1260359 [patent_doc_number] => 06668286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method and system for coordinating data and voice communications via customer contact channel changing system over IP' [patent_app_type] => B2 [patent_app_number] => 09/950801 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6465 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668286.pdf [firstpage_image] =>[orig_patent_app_number] => 09950801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950801
Method and system for coordinating data and voice communications via customer contact channel changing system over IP Sep 12, 2001 Issued
Array ( [id] => 6161601 [patent_doc_number] => 20020147935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Timer circuit' [patent_app_type] => new [patent_app_number] => 09/942587 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 19782 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20020147935.pdf [firstpage_image] =>[orig_patent_app_number] => 09942587 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942587
Timer circuit Aug 30, 2001 Abandoned
Array ( [id] => 1088654 [patent_doc_number] => 06832311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Information processing system and resume processing method used in the system' [patent_app_type] => B2 [patent_app_number] => 09/942751 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6690 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832311.pdf [firstpage_image] =>[orig_patent_app_number] => 09942751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942751
Information processing system and resume processing method used in the system Aug 30, 2001 Issued
Array ( [id] => 6484538 [patent_doc_number] => 20020152338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Method, system and program product for detecting lost sequences within an exchange on fibre channel' [patent_app_type] => new [patent_app_number] => 09/940215 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 32470 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20020152338.pdf [firstpage_image] =>[orig_patent_app_number] => 09940215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940215
Method, system and program product for detecting lost sequences within an exchange on fibre channel Aug 26, 2001 Abandoned
Array ( [id] => 947688 [patent_doc_number] => 06965989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'System and method for fast reboot of a file server' [patent_app_type] => utility [patent_app_number] => 09/929527 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6843 [patent_no_of_claims] => 71 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965989.pdf [firstpage_image] =>[orig_patent_app_number] => 09929527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929527
System and method for fast reboot of a file server Aug 13, 2001 Issued
Array ( [id] => 1043222 [patent_doc_number] => 06871290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Method for reducing a magnitude of a rate of current change of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/930373 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1464 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/871/06871290.pdf [firstpage_image] =>[orig_patent_app_number] => 09930373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930373
Method for reducing a magnitude of a rate of current change of an integrated circuit Aug 13, 2001 Issued
Array ( [id] => 1004695 [patent_doc_number] => 06910126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-21 [patent_title] => 'Programming methodology and architecture for a programmable analog system' [patent_app_type] => utility [patent_app_number] => 09/930021 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 47 [patent_no_of_words] => 10532 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910126.pdf [firstpage_image] =>[orig_patent_app_number] => 09930021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930021
Programming methodology and architecture for a programmable analog system Aug 13, 2001 Issued
Array ( [id] => 6839926 [patent_doc_number] => 20030037266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method and system for providing a flexible temperature design for a computer system' [patent_app_type] => new [patent_app_number] => 09/929807 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4036 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037266.pdf [firstpage_image] =>[orig_patent_app_number] => 09929807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929807
Method and system for providing a flexible temperature design for a computer system Aug 13, 2001 Issued
Array ( [id] => 7679292 [patent_doc_number] => 20030167360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Address assignment method for at least one bus device that has recently been connected to a bus system' [patent_app_type] => new [patent_app_number] => 10/344950 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1799 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20030167360.pdf [firstpage_image] =>[orig_patent_app_number] => 10344950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/344950
Address assignment method for at least one bus device that has recently been connected to a bus system Aug 5, 2001 Issued
Array ( [id] => 1185735 [patent_doc_number] => 06745259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-01 [patent_title] => 'OPEN NETWORK SYSTEM FOR I/O OPERATION INCLUDING A COMMON GATEWAY INTERFACE AND AN EXTENDED OPEN NETWORK PROTOCOL WITH NON-STANDARD I/O DEVICES UTILIZING DEVICE AND IDENTIFIER FOR OPERATION TO BE PERFORMED WITH DEVICE' [patent_app_type] => B2 [patent_app_number] => 09/907076 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 11388 [patent_no_of_claims] => 104 [patent_no_of_ind_claims] => 33 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745259.pdf [firstpage_image] =>[orig_patent_app_number] => 09907076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907076
OPEN NETWORK SYSTEM FOR I/O OPERATION INCLUDING A COMMON GATEWAY INTERFACE AND AN EXTENDED OPEN NETWORK PROTOCOL WITH NON-STANDARD I/O DEVICES UTILIZING DEVICE AND IDENTIFIER FOR OPERATION TO BE PERFORMED WITH DEVICE Jul 16, 2001 Issued
Array ( [id] => 1240808 [patent_doc_number] => 06691187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-10 [patent_title] => 'Printer-based interface with removable digital storage media' [patent_app_type] => B1 [patent_app_number] => 09/895186 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4863 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/691/06691187.pdf [firstpage_image] =>[orig_patent_app_number] => 09895186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895186
Printer-based interface with removable digital storage media Jul 1, 2001 Issued
Array ( [id] => 6606999 [patent_doc_number] => 20020042890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-11 [patent_title] => 'Digital microelectronic circuit with a clocked data-processing unit and a converting unit' [patent_app_type] => new [patent_app_number] => 09/888461 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1406 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20020042890.pdf [firstpage_image] =>[orig_patent_app_number] => 09888461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/888461
Digital microelectronic circuit with a clocked data-processing unit and a converting unit Jun 24, 2001 Issued
Array ( [id] => 1046370 [patent_doc_number] => 06868500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Power on reset circuit for a microcontroller' [patent_app_type] => utility [patent_app_number] => 09/887955 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6973 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868500.pdf [firstpage_image] =>[orig_patent_app_number] => 09887955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887955
Power on reset circuit for a microcontroller Jun 21, 2001 Issued
Array ( [id] => 6737047 [patent_doc_number] => 20030014682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Clock generation systems and methods' [patent_app_type] => new [patent_app_number] => 09/887905 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7163 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014682.pdf [firstpage_image] =>[orig_patent_app_number] => 09887905 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887905
Clock generation systems and methods Jun 21, 2001 Issued
Array ( [id] => 1062277 [patent_doc_number] => 06854067 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller' [patent_app_type] => utility [patent_app_number] => 09/887923 [patent_app_country] => US [patent_app_date] => 2001-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854067.pdf [firstpage_image] =>[orig_patent_app_number] => 09887923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887923
Method and system for interaction between a processor and a power on reset circuit to dynamically control power states in a microcontroller Jun 21, 2001 Issued
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