Search

Michael A. Band

Examiner (ID: 11521, Phone: (571)272-9815 , Office: P/1754 )

Most Active Art Unit
1794
Art Unit(s)
1795, 1723, 1794, 1754, 1753
Total Applications
970
Issued Applications
392
Pending Applications
91
Abandoned Applications
511

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19696397 [patent_doc_number] => 20250014942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR STACK STRUCTURE WITH ULTRA THIN DIE [patent_app_type] => utility [patent_app_number] => 18/893967 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18893967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/893967
Method for manufacturing semiconductor stack structure with ultra thin die Sep 23, 2024 Issued
Array ( [id] => 20146729 [patent_doc_number] => 12381076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Inherent area selective deposition of silicon-containing dielectric on metal substrate [patent_app_type] => utility [patent_app_number] => 18/791575 [patent_app_country] => US [patent_app_date] => 2024-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4664 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/791575
Inherent area selective deposition of silicon-containing dielectric on metal substrate Jul 31, 2024 Issued
Array ( [id] => 19546300 [patent_doc_number] => 20240363336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INTERCONNECT SYSTEM WITH IMPROVED LOW-K DIELECTRICS [patent_app_type] => utility [patent_app_number] => 18/771426 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9521 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771426 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771426
INTERCONNECT SYSTEM WITH IMPROVED LOW-K DIELECTRICS Jul 11, 2024 Pending
Array ( [id] => 19546525 [patent_doc_number] => 20240363561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INTEGRATED CIRCUIT FEATURES WITH OBTUSE ANGLES AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/768621 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768621 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768621
INTEGRATED CIRCUIT FEATURES WITH OBTUSE ANGLES AND METHOD OF FORMING SAME Jul 9, 2024 Pending
Array ( [id] => 19435999 [patent_doc_number] => 20240304497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => STRUCTURE FOR FRINGING CAPACITANCE CONTROL [patent_app_type] => utility [patent_app_number] => 18/667509 [patent_app_country] => US [patent_app_date] => 2024-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18667509 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/667509
STRUCTURE FOR FRINGING CAPACITANCE CONTROL May 16, 2024 Pending
Array ( [id] => 19407150 [patent_doc_number] => 20240290661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SLOT CONTACTS AND METHOD FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/655968 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655968
SLOT CONTACTS AND METHOD FORMING SAME May 5, 2024 Pending
Array ( [id] => 19392710 [patent_doc_number] => 20240282580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => MULTI-LAYER FEATURE FILL [patent_app_type] => utility [patent_app_number] => 18/655124 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655124 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655124
MULTI-LAYER FEATURE FILL May 2, 2024 Pending
Array ( [id] => 19321414 [patent_doc_number] => 20240242961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/619708 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12661 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619708 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619708
METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM Mar 27, 2024 Pending
Array ( [id] => 19364177 [patent_doc_number] => 20240266211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Selective Deposition of Barrier Layer [patent_app_type] => utility [patent_app_number] => 18/618044 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618044
Selective Deposition of Barrier Layer Mar 26, 2024 Pending
Array ( [id] => 20132226 [patent_doc_number] => 12374544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Processing method, method of manufacturing semiconductor device, processing apparatus, and recording medium [patent_app_type] => utility [patent_app_number] => 18/439018 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 16679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18439018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/439018
Processing method, method of manufacturing semiconductor device, processing apparatus, and recording medium Feb 11, 2024 Issued
Array ( [id] => 19208041 [patent_doc_number] => 20240179940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => DISPLAY SUBSTRATE AND PREPARATION METHOD THEREOF, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/433472 [patent_app_country] => US [patent_app_date] => 2024-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18433472 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/433472
DISPLAY SUBSTRATE AND PREPARATION METHOD THEREOF, AND DISPLAY DEVICE Feb 5, 2024 Pending
Array ( [id] => 20540524 [patent_doc_number] => 12557613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Silicon-on-insulator substrate including trap-rich layer and methods for making thereof [patent_app_type] => utility [patent_app_number] => 18/432778 [patent_app_country] => US [patent_app_date] => 2024-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 12106 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18432778 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/432778
Silicon-on-insulator substrate including trap-rich layer and methods for making thereof Feb 4, 2024 Issued
Array ( [id] => 19758182 [patent_doc_number] => 20250046747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 18/417810 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417810
SEMICONDUCTOR PACKAGE Jan 18, 2024 Pending
Array ( [id] => 20124274 [patent_doc_number] => 20250239305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE HAVING DIFFERENT SHAPE SUPPORT PILLAR STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/417130 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417130 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/417130
THREE-DIMENSIONAL MEMORY DEVICE HAVING DIFFERENT SHAPE SUPPORT PILLAR STRUCTURES Jan 18, 2024 Pending
Array ( [id] => 19252794 [patent_doc_number] => 20240203791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Integrated Circuitry, A Memory Array Comprising Strings Of Memory Cells, A Method Used In Forming A Conductive Via, A Method Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 18/416243 [patent_app_country] => US [patent_app_date] => 2024-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18416243 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/416243
Integrated circuitry, a memory array comprising strings of memory cells, a method used in forming a conductive via, a method used in forming a memory array comprising strings of memory cells Jan 17, 2024 Issued
Array ( [id] => 19161050 [patent_doc_number] => 20240153757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MANUFACTURING METHOD FOR SILICON NITRIDE THIN FILM, THIN FILM TRANSISTOR AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/412645 [patent_app_country] => US [patent_app_date] => 2024-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/412645
Manufacturing method for silicon nitride thin film, thin film transistor and display panel Jan 14, 2024 Issued
Array ( [id] => 19232748 [patent_doc_number] => 20240189940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => LASER-ASSISTED METHOD FOR PARTING CRYSTALLINE MATERIAL [patent_app_type] => utility [patent_app_number] => 18/411914 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 37221 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411914 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411914
LASER-ASSISTED METHOD FOR PARTING CRYSTALLINE MATERIAL Jan 11, 2024 Issued
Array ( [id] => 19886821 [patent_doc_number] => 12272548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method [patent_app_type] => utility [patent_app_number] => 18/410333 [patent_app_country] => US [patent_app_date] => 2024-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6071 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/410333
Method of forming an electronic structure using reforming gas, system for performing the method, and structure formed using the method Jan 10, 2024 Issued
Array ( [id] => 19161316 [patent_doc_number] => 20240154023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => RF SWITCH DEVICE WITH A SIDEWALL SPACER HAVING A LOW DIELECTRIC CONSTANT [patent_app_type] => utility [patent_app_number] => 18/402971 [patent_app_country] => US [patent_app_date] => 2024-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402971
RF switch device with a sidewall spacer having a low dielectric constant Jan 2, 2024 Issued
Array ( [id] => 19269422 [patent_doc_number] => 20240213126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/544774 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544774 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/544774
SEMICONDUCTOR DEVICE Dec 18, 2023 Pending
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