Michael Alsip

Array ( [id] => 4754904 [patent_doc_number] => 20080162980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Memory Controller Idle Mode' [patent_app_type] => utility [patent_app_number] => 11/948844 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162980.pdf [firstpage_image] =>[orig_patent_app_number] => 11948844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577131 [patent_doc_number] => 20090144493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Circular Buffer Maping' [patent_app_type] => utility [patent_app_number] => 11/948922 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144493.pdf [firstpage_image] =>[orig_patent_app_number] => 11948922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5577147 [patent_doc_number] => 20090144509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'MEMEORY SHARING BETWEEN TWO PROCESSORS' [patent_app_type] => utility [patent_app_number] => 11/948825 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10052 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144509.pdf [firstpage_image] =>[orig_patent_app_number] => 11948825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4440809 [patent_doc_number] => 07970993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Rotating parity redundant array of independent disk and method for storing parity the same' [patent_app_type] => utility [patent_app_number] => 11/987320 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5835 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/970/07970993.pdf [firstpage_image] =>[orig_patent_app_number] => 11987320 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 362547 [patent_doc_number] => 07487326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for managing metrics table per virtual port in a logically partitioned data processing system' [patent_app_type] => utility [patent_app_number] => 11/943441 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 14938 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487326.pdf [firstpage_image] =>[orig_patent_app_number] => 11943441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4722319 [patent_doc_number] => 20080244211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'MEMORY DEVICE AND CONTROLLER' [patent_app_type] => utility [patent_app_number] => 11/863832 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244211.pdf [firstpage_image] =>[orig_patent_app_number] => 11863832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4942761 [patent_doc_number] => 20080080084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Information leak-preventing apparatus and information leak-preventing method' [patent_app_type] => utility [patent_app_number] => 11/891997 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20080080084.pdf [firstpage_image] =>[orig_patent_app_number] => 11891997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 68893 [patent_doc_number] => 07761671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Data displacement bypass system' [patent_app_type] => utility [patent_app_number] => 11/838852 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 484 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761671.pdf [firstpage_image] =>[orig_patent_app_number] => 11838852 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4558689 [patent_doc_number] => 07877570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Consolidation of matching memory pages' [patent_app_type] => utility [patent_app_number] => 11/893269 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877570.pdf [firstpage_image] =>[orig_patent_app_number] => 11893269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8235448 [patent_doc_number] => 08200911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Device having shared memory and method for controlling shared memory' [patent_app_type] => utility [patent_app_number] => 12/307049 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9402 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/200/08200911.pdf [firstpage_image] =>[orig_patent_app_number] => 12307049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5292075 [patent_doc_number] => 20090024805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'System, method and computer-readable medium for enabling access to additional memory capacity' [patent_app_type] => utility [patent_app_number] => 11/879213 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5697 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024805.pdf [firstpage_image] =>[orig_patent_app_number] => 11879213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9714307 [patent_doc_number] => 08838909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Dynamic initial cache line coherency state assignment in multi-processor systems' [patent_app_type] => utility [patent_app_number] => 11/775085 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4707 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11775085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7993039 [patent_doc_number] => 08078827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method and apparatus for caching of page translations for virtual machines' [patent_app_type] => utility [patent_app_number] => 11/773747 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6630 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078827.pdf [firstpage_image] =>[orig_patent_app_number] => 11773747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5298202 [patent_doc_number] => 20090013128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Runtime Machine Supported Method Level Caching' [patent_app_type] => utility [patent_app_number] => 11/773462 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013128.pdf [firstpage_image] =>[orig_patent_app_number] => 11773462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8158113 [patent_doc_number] => 08171238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-01 [patent_title] => 'Identification of data stored in memory' [patent_app_type] => utility [patent_app_number] => 11/825440 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7699 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171238.pdf [firstpage_image] =>[orig_patent_app_number] => 11825440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4798840 [patent_doc_number] => 20080010426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'Processor system and processing method for operating system program in processor system' [patent_app_type] => utility [patent_app_number] => 11/822235 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20080010426.pdf [firstpage_image] =>[orig_patent_app_number] => 11822235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166611 [patent_doc_number] => 07673107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Storage system and storage control device' [patent_app_type] => utility [patent_app_number] => 11/773081 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 13400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 547 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673107.pdf [firstpage_image] =>[orig_patent_app_number] => 11773081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5350675 [patent_doc_number] => 20090006036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Shared, Low Cost and Featureable Performance Monitor Unit' [patent_app_type] => utility [patent_app_number] => 11/769005 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4789 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20090006036.pdf [firstpage_image] =>[orig_patent_app_number] => 11769005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 76337 [patent_doc_number] => 07757035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Method for optimizing virtualization technology and memory protections using processor-extensions for page table and page directory striping' [patent_app_type] => utility [patent_app_number] => 11/768344 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4748 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/757/07757035.pdf [firstpage_image] =>[orig_patent_app_number] => 11768344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8247122 [patent_doc_number] => 08205064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-19 [patent_title] => 'Latency hiding for a memory management unit page table lookup' [patent_app_type] => utility [patent_app_number] => 11/768375 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205064.pdf [firstpage_image] =>[orig_patent_app_number] => 11768375 [rel_patent_id] =>[rel_patent_doc_number] =>)