Michael Alsip

Array ( [id] => 5896404 [patent_doc_number] => 20060004943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Computer system for interleave memory accessing among a plurality of nodes' [patent_app_type] => utility [patent_app_number] => 11/167181 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2834 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20060004943.pdf [firstpage_image] =>[orig_patent_app_number] => 11167181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4448932 [patent_doc_number] => 07865684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Managing message queues' [patent_app_type] => utility [patent_app_number] => 11/169074 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 7742 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865684.pdf [firstpage_image] =>[orig_patent_app_number] => 11169074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5794997 [patent_doc_number] => 20060015678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Virtual memory device including a bridge circuit' [patent_app_type] => utility [patent_app_number] => 11/179006 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1599 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015678.pdf [firstpage_image] =>[orig_patent_app_number] => 11179006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 166608 [patent_doc_number] => 07673105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-02 [patent_title] => 'Managing memory pages' [patent_app_type] => utility [patent_app_number] => 11/169246 [patent_app_country] => US [patent_app_date] => 2005-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4932 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673105.pdf [firstpage_image] =>[orig_patent_app_number] => 11169246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5701681 [patent_doc_number] => 20060218366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Data relocation method' [patent_app_type] => utility [patent_app_number] => 11/130119 [patent_app_country] => US [patent_app_date] => 2005-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5104 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218366.pdf [firstpage_image] =>[orig_patent_app_number] => 11130119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 47693 [patent_doc_number] => 07783843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Bus interface adapted to coalesce snoop responses' [patent_app_type] => utility [patent_app_number] => 11/130536 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5246 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/783/07783843.pdf [firstpage_image] =>[orig_patent_app_number] => 11130536 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5734566 [patent_doc_number] => 20060259683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method and system for disk stippling' [patent_app_type] => utility [patent_app_number] => 11/131107 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4716 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259683.pdf [firstpage_image] =>[orig_patent_app_number] => 11131107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5679373 [patent_doc_number] => 20060184729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'Device, method, and computer product for disk management' [patent_app_type] => utility [patent_app_number] => 11/130462 [patent_app_country] => US [patent_app_date] => 2005-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2771 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20060184729.pdf [firstpage_image] =>[orig_patent_app_number] => 11130462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8010765 [patent_doc_number] => 08086800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-27 [patent_title] => 'Integrated circuit and method for buffering to optimize burst length in networks on chips' [patent_app_type] => utility [patent_app_number] => 11/569083 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4642 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 389 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/086/08086800.pdf [firstpage_image] =>[orig_patent_app_number] => 11569083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4754748 [patent_doc_number] => 20080162824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Orthogonal Data Memory' [patent_app_type] => utility [patent_app_number] => 10/591922 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7942 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20080162824.pdf [firstpage_image] =>[orig_patent_app_number] => 10591922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7993023 [patent_doc_number] => 08078818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method and system for migrating memory segments' [patent_app_type] => utility [patent_app_number] => 11/066038 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1933 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/078/08078818.pdf [firstpage_image] =>[orig_patent_app_number] => 11066038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 179980 [patent_doc_number] => 07657696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-02 [patent_title] => 'Method to detect NAND-flash parameters by hardware automatically' [patent_app_type] => utility [patent_app_number] => 11/067501 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6874 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/657/07657696.pdf [firstpage_image] =>[orig_patent_app_number] => 11067501 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5706575 [patent_doc_number] => 20060195623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Native virtualization on a partially trusted adapter using PCI host memory mapped input/output memory address for identification' [patent_app_type] => utility [patent_app_number] => 11/066487 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12836 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195623.pdf [firstpage_image] =>[orig_patent_app_number] => 11066487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5706626 [patent_doc_number] => 20060195674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'System and method for managing metrics table per virtual port in a logically partitioned data processing system' [patent_app_type] => utility [patent_app_number] => 11/066590 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 14954 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195674.pdf [firstpage_image] =>[orig_patent_app_number] => 11066590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5706615 [patent_doc_number] => 20060195663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Virtualized I/O adapter for a multi-processor data processing system' [patent_app_type] => utility [patent_app_number] => 11/066645 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 12260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195663.pdf [firstpage_image] =>[orig_patent_app_number] => 11066645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6946615 [patent_doc_number] => 20050198448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-08 [patent_title] => 'Self-administered shared virtual memory device, suitable for managing at least one multitrack data flow' [patent_app_type] => utility [patent_app_number] => 11/065092 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10396 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20050198448.pdf [firstpage_image] =>[orig_patent_app_number] => 11065092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5668713 [patent_doc_number] => 20060174063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Method of cooperative caching for distributed storage system' [patent_app_type] => utility [patent_app_number] => 11/051435 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3592 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174063.pdf [firstpage_image] =>[orig_patent_app_number] => 11051435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5668716 [patent_doc_number] => 20060174066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-03 [patent_title] => 'Fractional-word writable architected register for direct accumulation of misaligned data' [patent_app_type] => utility [patent_app_number] => 11/051037 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3306 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20060174066.pdf [firstpage_image] =>[orig_patent_app_number] => 11051037 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5657648 [patent_doc_number] => 20060143384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'System and method for non-uniform cache in a multi-core processor' [patent_app_type] => utility [patent_app_number] => 11/023925 [patent_app_country] => US [patent_app_date] => 2004-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5860 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143384.pdf [firstpage_image] =>[orig_patent_app_number] => 11023925 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5657675 [patent_doc_number] => 20060143411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Techniques to manage partition physical memory' [patent_app_type] => utility [patent_app_number] => 11/021323 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143411.pdf [firstpage_image] =>[orig_patent_app_number] => 11021323 [rel_patent_id] =>[rel_patent_doc_number] =>)