Michael C. Krofcheck

Array ( [id] => 20609977 [patent_doc_number] => 12585579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Locked raid with compression for memory interconnect applications [patent_app_type] => utility [patent_app_number] => 18/778627 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 12785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20867071 [patent_doc_number] => 12693965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Apparatuses and methods for controller signaling of refresh operations [patent_app_type] => utility [patent_app_number] => 18/774730 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1149 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19530360 [patent_doc_number] => 20240354262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => THE RELIABILITY OF COMPUTER MEMORY WITH DATA MOVEMENT AND ADDRESS RE-MAPPING [patent_app_type] => utility [patent_app_number] => 18/760305 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760305 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20102227 [patent_doc_number] => 20250232163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY CIRCUITS WITH MULTI-ROW STORAGE CELLS AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/757043 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20659098 [patent_doc_number] => 20260111141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => ATTRIBUTE VALUE DETERMINATION METHOD AND APPARATUS, NON-VOLATILE READABLE STORAGE MEDIUM AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 19/168935 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19168935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19544914 [patent_doc_number] => 20240361950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => HOST VERIFICATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/660070 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20624001 [patent_doc_number] => 12591509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Reconfigurable partitioning of high bandwidth memory [patent_app_type] => utility [patent_app_number] => 18/634147 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 10 [patent_no_of_words] => 6974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20123329 [patent_doc_number] => 20250238360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => SYSTEMS AND METHODS FOR MANAGING MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/630731 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20281900 [patent_doc_number] => 20250307142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => Arithmetic Logic Unit (ALU) in a Base Die of a Processing-in-Memory Component with Cross-ALU Data Communication Capability [patent_app_type] => utility [patent_app_number] => 18/622245 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283691 [patent_doc_number] => 20240220167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => System, Method, And Device for Uploading Data from Premises to Remote Computing Environments [patent_app_type] => utility [patent_app_number] => 18/605247 [patent_app_country] => US [patent_app_date] => 2024-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12059 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20214960 [patent_doc_number] => 12411612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Method of increasing flash endurance by improved metadata management [patent_app_type] => utility [patent_app_number] => 18/603941 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603941 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19303520 [patent_doc_number] => 20240232100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-ALIGNED WRITES [patent_app_type] => utility [patent_app_number] => 18/584151 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20145689 [patent_doc_number] => 12380032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Memory-aware pre-fetching and cache bypassing systems and methods [patent_app_type] => utility [patent_app_number] => 18/442676 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 24057 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19818900 [patent_doc_number] => 20250077107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => METHOD AND DEVICE FOR ACCESSING DATA IN HOST MEMORY [patent_app_type] => utility [patent_app_number] => 18/437583 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19250881 [patent_doc_number] => 20240201871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MEMORY SYSTEMS AND DEVICES INCLUDING EXAMPLES OF ACCESSING MEMORY AND GENERATING ACCESS CODES USING AN AUTHENTICATED STREAM CIPHER [patent_app_type] => utility [patent_app_number] => 18/428157 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11698 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20123115 [patent_doc_number] => 20250238146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => PROVIDING DATA STORAGE RESILIENCY [patent_app_type] => utility [patent_app_number] => 18/419806 [patent_app_country] => US [patent_app_date] => 2024-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18419806 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20145681 [patent_doc_number] => 12380024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Memory device, operating method of memory device, and storage device [patent_app_type] => utility [patent_app_number] => 18/417840 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9707 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19617244 [patent_doc_number] => 20240402924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SYSTEMS, METHODS, AND APPARATUS FOR CACHE CONFIGURATION BASED ON STORAGE PLACEMENT [patent_app_type] => utility [patent_app_number] => 18/418066 [patent_app_country] => US [patent_app_date] => 2024-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18418066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20094951 [patent_doc_number] => 20250224887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => VOLTAGE-ADAPTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 18/405412 [patent_app_country] => US [patent_app_date] => 2024-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18405412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19972229 [patent_doc_number] => 12340847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Flash memory chip that modulates its program step voltage as a function of chip temperature [patent_app_type] => utility [patent_app_number] => 18/402572 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402572 [rel_patent_id] =>[rel_patent_doc_number] =>)