Search

Michael C. Krofcheck

Examiner (ID: 1867, Phone: (571)272-8193 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2186, 2188, 2138
Total Applications
802
Issued Applications
636
Pending Applications
50
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6764056 [patent_doc_number] => 20030098454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SOLID-STATE IMAGE SENSOR' [patent_app_type] => new [patent_app_number] => 10/121699 [patent_app_country] => US [patent_app_date] => 2002-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5578 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098454.pdf [firstpage_image] =>[orig_patent_app_number] => 10121699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/121699
Semiconductor device having a solid-state image sensor Apr 14, 2002 Issued
Array ( [id] => 1385933 [patent_doc_number] => 06548367 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method to fabricate MIM capacitor with a curvillnear surface using damascene process' [patent_app_type] => B1 [patent_app_number] => 10/120105 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4039 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548367.pdf [firstpage_image] =>[orig_patent_app_number] => 10120105 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/120105
Method to fabricate MIM capacitor with a curvillnear surface using damascene process Apr 8, 2002 Issued
Array ( [id] => 1416179 [patent_doc_number] => 06509218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Front stage process of a fully depleted silicon-on-insulator device' [patent_app_type] => B2 [patent_app_number] => 10/119975 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3629 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509218.pdf [firstpage_image] =>[orig_patent_app_number] => 10119975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/119975
Front stage process of a fully depleted silicon-on-insulator device Apr 8, 2002 Issued
Array ( [id] => 6865264 [patent_doc_number] => 20030190790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Method of fabricating gate dielectric for use in semiconductor device' [patent_app_type] => new [patent_app_number] => 10/118046 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1443 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190790.pdf [firstpage_image] =>[orig_patent_app_number] => 10118046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/118046
Method of fabricating gate dielectric for use in semiconductor device having nitridation by ion implantation Apr 8, 2002 Issued
Array ( [id] => 1375229 [patent_doc_number] => 06558979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Use of palladium in IC manufacturing with conductive polymer bump' [patent_app_type] => B2 [patent_app_number] => 10/116962 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3756 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558979.pdf [firstpage_image] =>[orig_patent_app_number] => 10116962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/116962
Use of palladium in IC manufacturing with conductive polymer bump Apr 4, 2002 Issued
Array ( [id] => 1314191 [patent_doc_number] => 06614066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-02 [patent_title] => 'Ferroelectric transistor and memory cell configuration with the ferroelectric transistor' [patent_app_type] => B2 [patent_app_number] => 10/113418 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4531 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614066.pdf [firstpage_image] =>[orig_patent_app_number] => 10113418 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/113418
Ferroelectric transistor and memory cell configuration with the ferroelectric transistor Mar 31, 2002 Issued
Array ( [id] => 7632757 [patent_doc_number] => 06664577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-16 [patent_title] => 'Semiconductor device includes gate insulating film having a high dielectric constant' [patent_app_type] => B2 [patent_app_number] => 10/106345 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4113 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664577.pdf [firstpage_image] =>[orig_patent_app_number] => 10106345 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/106345
Semiconductor device includes gate insulating film having a high dielectric constant Mar 26, 2002 Issued
Array ( [id] => 788122 [patent_doc_number] => 06987054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Method of fabricating a semiconductor device having a groove formed in a resin layer' [patent_app_type] => utility [patent_app_number] => 10/097817 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 116 [patent_no_of_words] => 14567 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987054.pdf [firstpage_image] =>[orig_patent_app_number] => 10097817 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097817
Method of fabricating a semiconductor device having a groove formed in a resin layer Mar 14, 2002 Issued
Array ( [id] => 1570176 [patent_doc_number] => 06498057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method for implementing SOI transistor source connections using buried dual rail distribution' [patent_app_type] => B1 [patent_app_number] => 10/092748 [patent_app_country] => US [patent_app_date] => 2002-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2915 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498057.pdf [firstpage_image] =>[orig_patent_app_number] => 10092748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092748
Method for implementing SOI transistor source connections using buried dual rail distribution Mar 6, 2002 Issued
Array ( [id] => 1306651 [patent_doc_number] => 06617223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Semiconductor-on-insulator structure fabrication having a temporary plug' [patent_app_type] => B2 [patent_app_number] => 10/080136 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2654 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617223.pdf [firstpage_image] =>[orig_patent_app_number] => 10080136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080136
Semiconductor-on-insulator structure fabrication having a temporary plug Feb 20, 2002 Issued
Array ( [id] => 1395235 [patent_doc_number] => 06548839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability' [patent_app_type] => B1 [patent_app_number] => 10/079093 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1530 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548839.pdf [firstpage_image] =>[orig_patent_app_number] => 10079093 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079093
LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability Feb 19, 2002 Issued
Array ( [id] => 6740402 [patent_doc_number] => 20030157771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Method of forming an ultra-thin gate dielectric by soft plasma nitridation' [patent_app_type] => new [patent_app_number] => 10/077795 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1666 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20030157771.pdf [firstpage_image] =>[orig_patent_app_number] => 10077795 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077795
Method of forming an ultra-thin gate dielectric by soft plasma nitridation Feb 19, 2002 Abandoned
Array ( [id] => 1235661 [patent_doc_number] => 06689655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method for production process for the local interconnection level using a dielectric conducting pair on pair' [patent_app_type] => B2 [patent_app_number] => 10/081296 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 3652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689655.pdf [firstpage_image] =>[orig_patent_app_number] => 10081296 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081296
Method for production process for the local interconnection level using a dielectric conducting pair on pair Feb 19, 2002 Issued
Array ( [id] => 1347169 [patent_doc_number] => 06579766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Dual gate oxide process without critical resist and without N2 implant' [patent_app_type] => B1 [patent_app_number] => 10/077518 [patent_app_country] => US [patent_app_date] => 2002-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 22 [patent_no_of_words] => 3407 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579766.pdf [firstpage_image] =>[orig_patent_app_number] => 10077518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077518
Dual gate oxide process without critical resist and without N2 implant Feb 14, 2002 Issued
Array ( [id] => 6012309 [patent_doc_number] => 20020100932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method of forming a trench transistor having a superior gate dielectric' [patent_app_type] => new [patent_app_number] => 10/077258 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2789 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20020100932.pdf [firstpage_image] =>[orig_patent_app_number] => 10077258 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/077258
Method of forming a trench transistor having a superior gate dielectric Feb 13, 2002 Issued
Array ( [id] => 1231342 [patent_doc_number] => 06693007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Methods of utilizing a sacrificial layer during formation of a capacitor' [patent_app_type] => B2 [patent_app_number] => 10/076152 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 4357 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693007.pdf [firstpage_image] =>[orig_patent_app_number] => 10076152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/076152
Methods of utilizing a sacrificial layer during formation of a capacitor Feb 12, 2002 Issued
Array ( [id] => 6837173 [patent_doc_number] => 20030034513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Methods of forming a capacitor structure' [patent_app_type] => new [patent_app_number] => 10/075193 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4377 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034513.pdf [firstpage_image] =>[orig_patent_app_number] => 10075193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075193
Methods of forming a capacitor structure Feb 12, 2002 Issued
Array ( [id] => 6447304 [patent_doc_number] => 20020177286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method of producing SOI MOSFET' [patent_app_type] => new [patent_app_number] => 10/061356 [patent_app_country] => US [patent_app_date] => 2002-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5623 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177286.pdf [firstpage_image] =>[orig_patent_app_number] => 10061356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061356
Method of producing SOI MOSFET having threshold voltage of central and edge regions in opposite directions Feb 3, 2002 Issued
Array ( [id] => 6153859 [patent_doc_number] => 20020145173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Low voltage transistors with increased breakdown voltage to substrate' [patent_app_type] => new [patent_app_number] => 10/062215 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4573 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145173.pdf [firstpage_image] =>[orig_patent_app_number] => 10062215 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/062215
Method for making low voltage transistors with increased breakdown voltage to substrate having three different MOS transistors Jan 31, 2002 Issued
Array ( [id] => 1264389 [patent_doc_number] => 06660584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile' [patent_app_type] => B2 [patent_app_number] => 10/056183 [patent_app_country] => US [patent_app_date] => 2002-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5449 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660584.pdf [firstpage_image] =>[orig_patent_app_number] => 10056183 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/056183
Selective polysilicon stud growth of 6F2 memory cell manufacturing having a convex upper surface profile Jan 23, 2002 Issued
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