
Michael C. Krofcheck
Examiner (ID: 1867, Phone: (571)272-8193 , Office: P/2138 )
| Most Active Art Unit | 2138 |
| Art Unit(s) | 2186, 2188, 2138 |
| Total Applications | 802 |
| Issued Applications | 636 |
| Pending Applications | 50 |
| Abandoned Applications | 139 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6764056
[patent_doc_number] => 20030098454
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[patent_issue_date] => 2003-05-29
[patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SOLID-STATE IMAGE SENSOR'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/121699 | Semiconductor device having a solid-state image sensor | Apr 14, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-04-15
[patent_title] => 'Method to fabricate MIM capacitor with a curvillnear surface using damascene process'
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Array
(
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Array
(
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[patent_issue_date] => 2003-10-09
[patent_title] => 'Method of fabricating gate dielectric for use in semiconductor device'
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Array
(
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[patent_title] => 'Use of palladium in IC manufacturing with conductive polymer bump'
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Array
(
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[patent_title] => 'Ferroelectric transistor and memory cell configuration with the ferroelectric transistor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/113418 | Ferroelectric transistor and memory cell configuration with the ferroelectric transistor | Mar 31, 2002 | Issued |
Array
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[patent_title] => 'Semiconductor device includes gate insulating film having a high dielectric constant'
[patent_app_type] => B2
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Array
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[patent_title] => 'Method of fabricating a semiconductor device having a groove formed in a resin layer'
[patent_app_type] => utility
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Array
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[patent_title] => 'Method for implementing SOI transistor source connections using buried dual rail distribution'
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Array
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[patent_title] => 'Semiconductor-on-insulator structure fabrication having a temporary plug'
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Array
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[patent_title] => 'LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability'
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Array
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Array
(
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Array
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Array
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Array
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Array
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