Search

Michael C. Krofcheck

Examiner (ID: 605, Phone: (571)272-8193 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2138, 2186, 2188
Total Applications
816
Issued Applications
646
Pending Applications
49
Abandoned Applications
139

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18337306 [patent_doc_number] => 20230129255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => RELIABILITY OF COMPUTER MEMORY WITH DATA MOVEMENT AND ADDRESS RE-MAPPING [patent_app_type] => utility [patent_app_number] => 18/089879 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089879 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/089879
Prevention of RAM access pattern attacks via selective data movement Dec 27, 2022 Issued
Array ( [id] => 20117260 [patent_doc_number] => 12366963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Method for storing data and parity data in different chip enabled regions, memory storage device and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 18/088604 [patent_app_country] => US [patent_app_date] => 2022-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088604 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088604
Method for storing data and parity data in different chip enabled regions, memory storage device and memory control circuit unit Dec 24, 2022 Issued
Array ( [id] => 18966174 [patent_doc_number] => 11899942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher [patent_app_type] => utility [patent_app_number] => 18/146120 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18146120 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/146120
Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher Dec 22, 2022 Issued
Array ( [id] => 18614392 [patent_doc_number] => 20230281129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/066061 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066061 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066061
INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS CONTROL METHOD Dec 13, 2022 Abandoned
Array ( [id] => 19917469 [patent_doc_number] => 12292838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Host device performing near data processing function and accelerator system including the same [patent_app_type] => utility [patent_app_number] => 18/066161 [patent_app_country] => US [patent_app_date] => 2022-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 3247 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18066161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/066161
Host device performing near data processing function and accelerator system including the same Dec 13, 2022 Issued
Array ( [id] => 18741833 [patent_doc_number] => 20230350814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => DEVICE, METHOD AND SYSTEM TO SUPPLEMENT A CACHE WITH A RANDOMIZED VICTIM CACHE [patent_app_type] => utility [patent_app_number] => 18/078762 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078762 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078762
DEVICE, METHOD AND SYSTEM TO SUPPLEMENT A CACHE WITH A RANDOMIZED VICTIM CACHE Dec 8, 2022 Abandoned
Array ( [id] => 19942053 [patent_doc_number] => 12314182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Updating related data in multi-cache systems [patent_app_type] => utility [patent_app_number] => 18/064020 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11984 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064020
Updating related data in multi-cache systems Dec 8, 2022 Issued
Array ( [id] => 18286477 [patent_doc_number] => 20230101949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => DEVICE AND METHOD FOR SHARED MEMORY PROCESSING AND NON-TRANSITORY COMPUTER STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/063298 [patent_app_country] => US [patent_app_date] => 2022-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18063298 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/063298
DEVICE AND METHOD FOR SHARED MEMORY PROCESSING AND NON-TRANSITORY COMPUTER STORAGE MEDIUM Dec 7, 2022 Abandoned
Array ( [id] => 19669269 [patent_doc_number] => 12182016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-31 [patent_title] => Memory circuit with power registers [patent_app_type] => utility [patent_app_number] => 17/981666 [patent_app_country] => US [patent_app_date] => 2022-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11269 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17981666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/981666
Memory circuit with power registers Nov 6, 2022 Issued
Array ( [id] => 19781316 [patent_doc_number] => 12230354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Apparatuses and methods for scatter and gather [patent_app_type] => utility [patent_app_number] => 17/971300 [patent_app_country] => US [patent_app_date] => 2022-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 11969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17971300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/971300
Apparatuses and methods for scatter and gather Oct 20, 2022 Issued
Array ( [id] => 20828300 [patent_doc_number] => 12681869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Method for locking a rewritable non-volatile memory and electronic device implementing said method [patent_app_type] => utility [patent_app_number] => 17/969948 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17969948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/969948
Method for locking a rewritable non-volatile memory and electronic device implementing said method Oct 19, 2022 Issued
Array ( [id] => 19122648 [patent_doc_number] => 11966637 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-04-23 [patent_title] => Method and system for storing data in portable storage devices [patent_app_type] => utility [patent_app_number] => 17/961732 [patent_app_country] => US [patent_app_date] => 2022-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17961732 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/961732
Method and system for storing data in portable storage devices Oct 6, 2022 Issued
Array ( [id] => 18149196 [patent_doc_number] => 20230023053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => DATA LOSS RECOVERY IN A SECONDARY STORAGE CONTROLLER FROM A PRIMARY STORAGE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/959970 [patent_app_country] => US [patent_app_date] => 2022-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17959970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/959970
Data loss recovery in a secondary storage controller from a primary storage controller Oct 3, 2022 Issued
Array ( [id] => 18180633 [patent_doc_number] => 20230041362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => Memory Controller with Programmable Atomic Operations [patent_app_type] => utility [patent_app_number] => 17/958404 [patent_app_country] => US [patent_app_date] => 2022-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25281 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17958404 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/958404
Memory controller with programmable atomic operations Oct 1, 2022 Issued
Array ( [id] => 18734752 [patent_doc_number] => 11803483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Metadata cache for storing manifest portion [patent_app_type] => utility [patent_app_number] => 17/935368 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17935368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/935368
Metadata cache for storing manifest portion Sep 25, 2022 Issued
Array ( [id] => 19732467 [patent_doc_number] => 12210463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Aggressive write flush scheme for a victim cache [patent_app_type] => utility [patent_app_number] => 17/941587 [patent_app_country] => US [patent_app_date] => 2022-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 26331 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17941587 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/941587
Aggressive write flush scheme for a victim cache Sep 8, 2022 Issued
Array ( [id] => 19021844 [patent_doc_number] => 20240078015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => HANDLING WRITE DATA BURST FOR IMPROVED PERFORMANCE AND RESOURCE USAGE [patent_app_type] => utility [patent_app_number] => 17/901719 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901719
Handling write data burst for improved performance and resource usage Aug 31, 2022 Issued
Array ( [id] => 19493059 [patent_doc_number] => 12111770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Silent cache line eviction [patent_app_type] => utility [patent_app_number] => 17/823408 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11564 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823408
Silent cache line eviction Aug 29, 2022 Issued
Array ( [id] => 18095429 [patent_doc_number] => 20220413770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => METHOD FOR CONTROLLING WRITE AND READ OPERATIONS IN THE NONVOLATILE MEMORY BY A HOST, USING AN IDENTIFIER FOR A REGION [patent_app_type] => utility [patent_app_number] => 17/898774 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898774 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898774
Method for controlling write and read operations in the nonvolatile memory by a host, using an identifier for a region Aug 29, 2022 Issued
Array ( [id] => 18694693 [patent_doc_number] => 20230325109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/898791 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898791 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898791
Memory system that manages wear-out information of its non-volatile memory according to an operation mode of the non-volatile memory and method of operating the memory system Aug 29, 2022 Issued
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