Search

Michael C. Stout

Examiner (ID: 7751, Phone: (408)918-7558 , Office: P/3736 )

Most Active Art Unit
3736
Art Unit(s)
3736, 2910, 2924, 4123
Total Applications
565
Issued Applications
352
Pending Applications
4
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7819864 [patent_doc_number] => 20120066484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'PATCHING METHOD AND PATCHING DEVICE IN MULTI-CORE ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/300330 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9972 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066484.pdf [firstpage_image] =>[orig_patent_app_number] => 13300330 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/300330
PATCHING METHOD AND PATCHING DEVICE IN MULTI-CORE ENVIRONMENT Nov 17, 2011 Abandoned
Array ( [id] => 7785796 [patent_doc_number] => 20120047352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/285137 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6452 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20120047352.pdf [firstpage_image] =>[orig_patent_app_number] => 13285137 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285137
PROCESSOR Oct 30, 2011 Abandoned
Array ( [id] => 10092233 [patent_doc_number] => 09129060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-08 [patent_title] => 'QoS based dynamic execution engine selection' [patent_app_type] => utility [patent_app_number] => 13/272975 [patent_app_country] => US [patent_app_date] => 2011-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6077 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13272975 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/272975
QoS based dynamic execution engine selection Oct 12, 2011 Issued
Array ( [id] => 8746650 [patent_doc_number] => 20130086367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Tracking operand liveliness information in a computer system and performance function based on the liveliness information' [patent_app_type] => utility [patent_app_number] => 13/251441 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 18247 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251441 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251441
Tracking operand liveness information in a computer system and performing function based on the liveness information Oct 2, 2011 Issued
Array ( [id] => 9150496 [patent_doc_number] => 20130305019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Instruction and Logic to Control Transfer in a Partial Binary Translation System' [patent_app_type] => utility [patent_app_number] => 13/996352 [patent_app_country] => US [patent_app_date] => 2011-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11786 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996352 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996352
Instruction and logic to control transfer in a partial binary translation system Sep 29, 2011 Issued
Array ( [id] => 8746642 [patent_doc_number] => 20130086359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Processor Hardware Pipeline Configured for Single-Instruction Address Extraction and Memory Access Operation' [patent_app_type] => utility [patent_app_number] => 13/248329 [patent_app_country] => US [patent_app_date] => 2011-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4833 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13248329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/248329
Processor Hardware Pipeline Configured for Single-Instruction Address Extraction and Memory Access Operation Sep 28, 2011 Abandoned
Array ( [id] => 11179592 [patent_doc_number] => 09411585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Multi-addressable register files and format conversions associated therewith' [patent_app_type] => utility [patent_app_number] => 13/234520 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 17095 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/234520
Multi-addressable register files and format conversions associated therewith Sep 15, 2011 Issued
Array ( [id] => 10027664 [patent_doc_number] => 09069563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Reducing store-hit-loads in an out-of-order processor' [patent_app_type] => utility [patent_app_number] => 13/235174 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13235174 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/235174
Reducing store-hit-loads in an out-of-order processor Sep 15, 2011 Issued
Array ( [id] => 9878933 [patent_doc_number] => 08966229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Systems and methods for handling instructions of in-order and out-of-order execution queues' [patent_app_type] => utility [patent_app_number] => 13/212420 [patent_app_country] => US [patent_app_date] => 2011-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7824 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13212420 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/212420
Systems and methods for handling instructions of in-order and out-of-order execution queues Aug 17, 2011 Issued
Array ( [id] => 8672418 [patent_doc_number] => 20130046956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS OF IN-ORDER AND OUT-OF-ORDER EXECUTION QUEUES' [patent_app_type] => utility [patent_app_number] => 13/210566 [patent_app_country] => US [patent_app_date] => 2011-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/210566
Systems and methods for handling instructions of in-order and out-of-order execution queues Aug 15, 2011 Issued
Array ( [id] => 8672423 [patent_doc_number] => 20130046961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SPECULATIVE MEMORY WRITE IN A PIPELINED PROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/209681 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209681 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209681
SPECULATIVE MEMORY WRITE IN A PIPELINED PROCESSOR Aug 14, 2011 Abandoned
Array ( [id] => 8672426 [patent_doc_number] => 20130046964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'SYSTEM AND METHOD FOR ZERO PENALTY BRANCH MIS-PREDICTIONS' [patent_app_type] => utility [patent_app_number] => 13/209484 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209484
SYSTEM AND METHOD FOR ZERO PENALTY BRANCH MIS-PREDICTIONS Aug 14, 2011 Abandoned
Array ( [id] => 8176593 [patent_doc_number] => 20120110307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'COMPRESSED INSTRUCTION PROCESSING DEVICE AND COMPRESSED INSTRUCTION GENERATION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/209843 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6587 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110307.pdf [firstpage_image] =>[orig_patent_app_number] => 13209843 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209843
COMPRESSED INSTRUCTION PROCESSING DEVICE AND COMPRESSED INSTRUCTION GENERATION DEVICE Aug 14, 2011 Abandoned
Array ( [id] => 8661261 [patent_doc_number] => 20130042090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'TEMPORAL SIMT EXECUTION OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 13/209189 [patent_app_country] => US [patent_app_date] => 2011-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13209189 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/209189
Temporal SIMT execution optimization through elimination of redundant operations Aug 11, 2011 Issued
Array ( [id] => 8661260 [patent_doc_number] => 20130042089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'WORD LINE LATE KILL IN SCHEDULER' [patent_app_type] => utility [patent_app_number] => 13/207724 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207724 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207724
WORD LINE LATE KILL IN SCHEDULER Aug 10, 2011 Abandoned
Array ( [id] => 8059035 [patent_doc_number] => 20120079254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'Debugging of a data processing apparatus' [patent_app_type] => utility [patent_app_number] => 13/137375 [patent_app_country] => US [patent_app_date] => 2011-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10272 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20120079254.pdf [firstpage_image] =>[orig_patent_app_number] => 13137375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137375
Debug instruction set allocation according to processor operating state Aug 9, 2011 Issued
Array ( [id] => 10143930 [patent_doc_number] => 09176739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions' [patent_app_type] => utility [patent_app_number] => 13/204346 [patent_app_country] => US [patent_app_date] => 2011-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7264 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13204346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/204346
System and method for checking run-time consistency for sequentially and non-sequentially fetched instructions Aug 4, 2011 Issued
Array ( [id] => 9826020 [patent_doc_number] => 08935516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured' [patent_app_type] => utility [patent_app_number] => 13/193761 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4175 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193761 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193761
Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured Jul 28, 2011 Issued
Array ( [id] => 8485082 [patent_doc_number] => 20120284489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'Methods and Apparatus for Constant Extension in a Processor' [patent_app_type] => utility [patent_app_number] => 13/155565 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8315 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13155565 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/155565
Methods and Apparatus for Constant Extension in a Processor Jun 7, 2011 Abandoned
Array ( [id] => 10517724 [patent_doc_number] => 09244772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Computer processor providing error recovery with idempotent regions' [patent_app_type] => utility [patent_app_number] => 13/100517 [patent_app_country] => US [patent_app_date] => 2011-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5489 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13100517 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100517
Computer processor providing error recovery with idempotent regions May 3, 2011 Issued
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