Search

Michael C. Stout

Examiner (ID: 7751, Phone: (408)918-7558 , Office: P/3736 )

Most Active Art Unit
3736
Art Unit(s)
3736, 2910, 2924, 4123
Total Applications
565
Issued Applications
352
Pending Applications
4
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11530964 [patent_doc_number] => 20170090942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'HETEROGENEOUS CORE MICROARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/242764 [patent_app_country] => US [patent_app_date] => 2016-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4261 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15242764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/242764
Heterogeneous core microarchitecture Aug 21, 2016 Issued
Array ( [id] => 14952983 [patent_doc_number] => 10437756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Operation of a multi-slice processor implementing datapath steering [patent_app_type] => utility [patent_app_number] => 15/220780 [patent_app_country] => US [patent_app_date] => 2016-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7154 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15220780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/220780
Operation of a multi-slice processor implementing datapath steering Jul 26, 2016 Issued
Array ( [id] => 12094430 [patent_doc_number] => 20170351523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING' [patent_app_type] => utility [patent_app_number] => 15/172635 [patent_app_country] => US [patent_app_date] => 2016-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15172635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/172635
Operation of a multi-slice processor implementing datapath steering Jun 2, 2016 Issued
Array ( [id] => 12842971 [patent_doc_number] => 20180172830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => DISTANCE IMAGE PROCESSING DEVICE, DISTANCE IMAGE PROCESSING METHOD, DISTANCE IMAGE PROCESSING PROGRAM, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 15/737032 [patent_app_country] => US [patent_app_date] => 2016-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15737032 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/737032
DISTANCE IMAGE PROCESSING DEVICE, DISTANCE IMAGE PROCESSING METHOD, DISTANCE IMAGE PROCESSING PROGRAM, AND RECORDING MEDIUM May 24, 2016 Abandoned
Array ( [id] => 14601035 [patent_doc_number] => 10353710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Techniques for predicting a target address of an indirect branch instruction [patent_app_type] => utility [patent_app_number] => 15/141112 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10667 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141112
Techniques for predicting a target address of an indirect branch instruction Apr 27, 2016 Issued
Array ( [id] => 13817591 [patent_doc_number] => 10185564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Method for managing software threads dependent on condition variables [patent_app_type] => utility [patent_app_number] => 15/141428 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141428
Method for managing software threads dependent on condition variables Apr 27, 2016 Issued
Array ( [id] => 11042449 [patent_doc_number] => 20160239405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'DEBUGGING OF A DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/140514 [patent_app_country] => US [patent_app_date] => 2016-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10304 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15140514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/140514
Allocating a debug instruction set based on the current operating state in a multi-instruction-set data processing apparatus Apr 27, 2016 Issued
Array ( [id] => 14735581 [patent_doc_number] => 10387190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => System and method of executing a plurality of threads using thread switching on execution time-out using instruction re-write [patent_app_type] => utility [patent_app_number] => 15/139991 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5528 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139991 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139991
System and method of executing a plurality of threads using thread switching on execution time-out using instruction re-write Apr 26, 2016 Issued
Array ( [id] => 13817599 [patent_doc_number] => 10185568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Annotation logic for dynamic instruction lookahead distance determination [patent_app_type] => utility [patent_app_number] => 15/136123 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15136123 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/136123
Annotation logic for dynamic instruction lookahead distance determination Apr 21, 2016 Issued
Array ( [id] => 11258423 [patent_doc_number] => 09483322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Heterogenous core microarchitecture' [patent_app_type] => utility [patent_app_number] => 15/135779 [patent_app_country] => US [patent_app_date] => 2016-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4263 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 413 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15135779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/135779
Heterogenous core microarchitecture Apr 21, 2016 Issued
Array ( [id] => 11745666 [patent_doc_number] => 20170199739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'INSTRUCTION PREFETCHER DYNAMICALLY CONTROLLED BY READILY AVAILABLE PREFETCHER ACCURACY' [patent_app_type] => utility [patent_app_number] => 15/132230 [patent_app_country] => US [patent_app_date] => 2016-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15132230 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/132230
Instruction prefetcher dynamically controlled by readily available prefetcher accuracy Apr 17, 2016 Issued
Array ( [id] => 11027384 [patent_doc_number] => 20160224341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'EXTENSIBLE EXECUTION UNIT INTERFACE ARCHITECTURE WITH MULTIPLE DECODE LOGIC AND MULTIPLE EXECUTION UNITS' [patent_app_type] => utility [patent_app_number] => 15/095780 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095780 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095780
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Apr 10, 2016 Issued
Array ( [id] => 11027386 [patent_doc_number] => 20160224342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'EXTENSIBLE EXECUTION UNIT INTERFACE ARCHITECTURE WITH MULTIPLE DECODE LOGIC AND MULTIPLE EXECUTION UNITS' [patent_app_type] => utility [patent_app_number] => 15/095799 [patent_app_country] => US [patent_app_date] => 2016-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15095799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/095799
Extensible execution unit interface architecture with multiple decode logic and multiple execution units Apr 10, 2016 Issued
Array ( [id] => 13860045 [patent_doc_number] => 10191741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => System and method for mitigating the impact of branch misprediction when exiting spin loops [patent_app_type] => utility [patent_app_number] => 15/090554 [patent_app_country] => US [patent_app_date] => 2016-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15090554 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/090554
System and method for mitigating the impact of branch misprediction when exiting spin loops Apr 3, 2016 Issued
Array ( [id] => 11445139 [patent_doc_number] => 20170046160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'EFFICIENT HANDLING OF REGISTER FILES' [patent_app_type] => utility [patent_app_number] => 15/086055 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7620 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15086055 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/086055
EFFICIENT HANDLING OF REGISTER FILES Mar 30, 2016 Abandoned
Array ( [id] => 13143561 [patent_doc_number] => 10089114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-02 [patent_title] => Multiple instruction issuance with parallel inter-group and intra-group picking [patent_app_type] => utility [patent_app_number] => 15/086052 [patent_app_country] => US [patent_app_date] => 2016-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6595 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15086052 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/086052
Multiple instruction issuance with parallel inter-group and intra-group picking Mar 29, 2016 Issued
Array ( [id] => 10982592 [patent_doc_number] => 20160179536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'Early termination of segment monitoring in run-time code parallelization' [patent_app_type] => utility [patent_app_number] => 15/007299 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7316 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15007299 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/007299
Early termination of segment monitoring in run-time code parallelization Jan 26, 2016 Issued
Array ( [id] => 11584728 [patent_doc_number] => 09639370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-02 [patent_title] => 'Software instructed dynamic branch history pattern adjustment' [patent_app_type] => utility [patent_app_number] => 14/969294 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6771 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969294 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969294
Software instructed dynamic branch history pattern adjustment Dec 14, 2015 Issued
Array ( [id] => 11299590 [patent_doc_number] => 09507598 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-29 [patent_title] => 'Auxiliary branch prediction with usefulness tracking' [patent_app_type] => utility [patent_app_number] => 14/969492 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8530 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969492 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969492
Auxiliary branch prediction with usefulness tracking Dec 14, 2015 Issued
Array ( [id] => 11006030 [patent_doc_number] => 20160202980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'MICROPROCESSOR WITH ARM AND X86 INSTRUCTION LENGTH DECODERS' [patent_app_type] => utility [patent_app_number] => 14/963134 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18724 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963134 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/963134
Microprocessor with arm and X86 instruction length decoders Dec 7, 2015 Issued
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