Search

Michael Collins

Examiner (ID: 13825, Phone: (571)272-8970 , Office: P/3651 )

Most Active Art Unit
3651
Art Unit(s)
3655, 3651
Total Applications
1512
Issued Applications
1008
Pending Applications
131
Abandoned Applications
411

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10551564 [patent_doc_number] => 09276198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-01 [patent_title] => 'Magnetic memory devices' [patent_app_type] => utility [patent_app_number] => 13/967340 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11552 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13967340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/967340
Magnetic memory devices Aug 13, 2013 Issued
Array ( [id] => 10028852 [patent_doc_number] => 09070761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-30 [patent_title] => 'Field effect transistor (FET) having fingers with rippled edges' [patent_app_type] => utility [patent_app_number] => 13/966400 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966400 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966400
Field effect transistor (FET) having fingers with rippled edges Aug 13, 2013 Issued
Array ( [id] => 9802770 [patent_doc_number] => 20150014715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-15 [patent_title] => 'WHITE LIGHT LED MODULE STRUCTURE INCLUDING ULTRAVIOLET LIGHT' [patent_app_type] => utility [patent_app_number] => 13/966674 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3200 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966674 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966674
WHITE LIGHT LED MODULE STRUCTURE INCLUDING ULTRAVIOLET LIGHT Aug 13, 2013 Abandoned
Array ( [id] => 9768022 [patent_doc_number] => 20140291684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'DISPLAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/966844 [patent_app_country] => US [patent_app_date] => 2013-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3794 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13966844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/966844
Display substrate Aug 13, 2013 Issued
Array ( [id] => 9893286 [patent_doc_number] => 20150048484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer' [patent_app_type] => utility [patent_app_number] => 13/965567 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7324 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965567 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965567
Passivation for group III-V semiconductor devices having a plated metal layer over an interlayer dielectric layer Aug 12, 2013 Issued
Array ( [id] => 9145302 [patent_doc_number] => 20130299825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'DISPLAY DEVICE HAVING AN OXIDE SEMICONDUCTOR TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/944996 [patent_app_country] => US [patent_app_date] => 2013-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15324 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13944996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/944996
Display device having an oxide semiconductor transistor Jul 17, 2013 Issued
Array ( [id] => 9132052 [patent_doc_number] => 20130292765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A DRAIN-GATE ISOLATION PORTION' [patent_app_type] => utility [patent_app_number] => 13/941458 [patent_app_country] => US [patent_app_date] => 2013-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5039 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13941458 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/941458
Semiconductor device having a drain-gate isolation portion Jul 12, 2013 Issued
Array ( [id] => 9882398 [patent_doc_number] => 08969162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-03 [patent_title] => 'Three-dimensional semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 13/933772 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 11385 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933772
Three-dimensional semiconductor device and method for fabricating the same Jul 1, 2013 Issued
Array ( [id] => 9889368 [patent_doc_number] => 08975625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-10 [patent_title] => 'TFT with insert in passivation layer or etch stop layer' [patent_app_type] => utility [patent_app_number] => 13/932340 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3397 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932340
TFT with insert in passivation layer or etch stop layer Jun 30, 2013 Issued
Array ( [id] => 9209589 [patent_doc_number] => 20140008766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-09 [patent_title] => 'EPITAXIAL STRUCTURE AND EPITAXIAL GROWTH METHOD FOR FORMING EPITAXIAL LAYER WITH CAVITIES' [patent_app_type] => utility [patent_app_number] => 13/932665 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3501 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932665 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932665
Epitaxial structure and epitaxial growth method for forming epitaxial layer with cavities Jun 30, 2013 Issued
Array ( [id] => 10132022 [patent_doc_number] => 09165863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-20 [patent_title] => 'Systems and methods for lead frame locking design features' [patent_app_type] => utility [patent_app_number] => 13/932076 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 5798 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932076
Systems and methods for lead frame locking design features Jun 30, 2013 Issued
Array ( [id] => 9789726 [patent_doc_number] => 20150001670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-01-01 [patent_title] => 'Semiconductor structure and method of forming a harmonic-effect-suppression structure' [patent_app_type] => utility [patent_app_number] => 13/932009 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3909 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932009 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932009
Semiconductor structure and method of forming a harmonic-effect-suppression structure Jun 30, 2013 Issued
Array ( [id] => 9749700 [patent_doc_number] => 08841174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-23 [patent_title] => 'Silicon controlled rectifier with integral deep trench capacitor' [patent_app_type] => utility [patent_app_number] => 13/932132 [patent_app_country] => US [patent_app_date] => 2013-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6211 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13932132 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/932132
Silicon controlled rectifier with integral deep trench capacitor Jun 30, 2013 Issued
Array ( [id] => 10518900 [patent_doc_number] => 09245955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'Embedded shape SiGe for strained channel transistors' [patent_app_type] => utility [patent_app_number] => 13/931509 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4769 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931509 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/931509
Embedded shape SiGe for strained channel transistors Jun 27, 2013 Issued
Array ( [id] => 10943513 [patent_doc_number] => 20140346534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-27 [patent_title] => 'PIXEL UNIT AND AN ARRAY SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/985693 [patent_app_country] => US [patent_app_date] => 2013-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13985693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/985693
PIXEL UNIT AND AN ARRAY SUBSTRATE Jun 26, 2013 Abandoned
Array ( [id] => 9876015 [patent_doc_number] => 08963287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-02-24 [patent_title] => 'Deep trench capacitor with conformally-deposited conductive layers having compressive stress' [patent_app_type] => utility [patent_app_number] => 13/925934 [patent_app_country] => US [patent_app_date] => 2013-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6718 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925934 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/925934
Deep trench capacitor with conformally-deposited conductive layers having compressive stress Jun 24, 2013 Issued
Array ( [id] => 10536123 [patent_doc_number] => 09261750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Array substrate, method for fabricating the same and liquid crystal panel' [patent_app_type] => utility [patent_app_number] => 14/368134 [patent_app_country] => US [patent_app_date] => 2013-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4199 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14368134 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/368134
Array substrate, method for fabricating the same and liquid crystal panel Jun 4, 2013 Issued
Array ( [id] => 9938050 [patent_doc_number] => 08987863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Electrical components for microelectronic devices and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 13/903364 [patent_app_country] => US [patent_app_date] => 2013-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3904 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13903364 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/903364
Electrical components for microelectronic devices and methods of forming the same May 27, 2013 Issued
Array ( [id] => 10556995 [patent_doc_number] => 09281198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes' [patent_app_type] => utility [patent_app_number] => 13/900808 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5751 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13900808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/900808
Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes May 22, 2013 Issued
Array ( [id] => 9065018 [patent_doc_number] => 20130256775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'THREE-DIMENSIONAL MICROELECTRONIC DEVICES INCLUDING HORIZONTAL AND VERTICAL PATTERNS' [patent_app_type] => utility [patent_app_number] => 13/901205 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 9236 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901205 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/901205
Three-dimensional microelectronic devices including horizontal and vertical patterns May 22, 2013 Issued
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