
Michael D. Allen
Examiner (ID: 12829, Phone: (571)270-3497 , Office: P/1642 )
| Most Active Art Unit | 1642 |
| Art Unit(s) | 1671, 1642 |
| Total Applications | 616 |
| Issued Applications | 166 |
| Pending Applications | 78 |
| Abandoned Applications | 397 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19470553
[patent_doc_number] => 20240324223
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES
[patent_app_type] => utility
[patent_app_number] => 18/731940
[patent_app_country] => US
[patent_app_date] => 2024-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7342
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731940
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/731940 | INTEGRATED ASSEMBLIES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES | Jun 2, 2024 | Pending |
Array
(
[id] => 19452705
[patent_doc_number] => 20240312835
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/675406
[patent_app_country] => US
[patent_app_date] => 2024-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6346
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675406
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/675406 | Semiconductor device structure and methods of forming the same | May 27, 2024 | Issued |
Array
(
[id] => 19467965
[patent_doc_number] => 20240321635
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => ETCH STOP LAYER FOR MEMORY DEVICE FORMATION
[patent_app_type] => utility
[patent_app_number] => 18/668329
[patent_app_country] => US
[patent_app_date] => 2024-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9892
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668329
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668329 | Etch stop layer for memory device formation | May 19, 2024 | Issued |
Array
(
[id] => 20375300
[patent_doc_number] => 12482744
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Subtractively patterned interconnect structures for integrated circuits
[patent_app_type] => utility
[patent_app_number] => 18/668038
[patent_app_country] => US
[patent_app_date] => 2024-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 55
[patent_figures_cnt] => 114
[patent_no_of_words] => 30568
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668038
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/668038 | Subtractively patterned interconnect structures for integrated circuits | May 16, 2024 | Issued |
Array
(
[id] => 19577397
[patent_doc_number] => 20240381689
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-14
[patent_title] => ELECTRONIC DEVICE HAVING AN ORGANIC LIGHT EMITTING DISPLAY
[patent_app_type] => utility
[patent_app_number] => 18/664533
[patent_app_country] => US
[patent_app_date] => 2024-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5291
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664533
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/664533 | ELECTRONIC DEVICE HAVING AN ORGANIC LIGHT EMITTING DISPLAY | May 14, 2024 | Pending |
Array
(
[id] => 19436074
[patent_doc_number] => 20240304572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 18/664508
[patent_app_country] => US
[patent_app_date] => 2024-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16857
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664508
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/664508 | Semiconductor device and method of manufacture | May 14, 2024 | Issued |
Array
(
[id] => 19407142
[patent_doc_number] => 20240290653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP
[patent_app_type] => utility
[patent_app_number] => 18/655495
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655495
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655495 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP | May 5, 2024 | Pending |
Array
(
[id] => 19407142
[patent_doc_number] => 20240290653
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP
[patent_app_type] => utility
[patent_app_number] => 18/655495
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655495
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655495 | INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARRIER LAYER AND AIR GAP | May 5, 2024 | Pending |
Array
(
[id] => 19407143
[patent_doc_number] => 20240290654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => Polishing Interconnect Structures In Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 18/655763
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8497
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655763
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655763 | Polishing Interconnect Structures In Semiconductor Devices | May 5, 2024 | Issued |
Array
(
[id] => 19407143
[patent_doc_number] => 20240290654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-29
[patent_title] => Polishing Interconnect Structures In Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 18/655763
[patent_app_country] => US
[patent_app_date] => 2024-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8497
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655763
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/655763 | Polishing Interconnect Structures In Semiconductor Devices | May 5, 2024 | Issued |
Array
(
[id] => 19349271
[patent_doc_number] => 20240258235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE CONTACTS OF DIFFERENT WIDTHS AND METHOD FOR PREPARING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/635387
[patent_app_country] => US
[patent_app_date] => 2024-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7067
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635387
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/635387 | Semiconductor device structure with conductive contacts of different widths and method for preparing the same | Apr 14, 2024 | Issued |
Array
(
[id] => 19906484
[patent_doc_number] => 12283500
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => Methods and systems for temperature control for a substrate
[patent_app_type] => utility
[patent_app_number] => 18/634628
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6931
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634628
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634628 | Methods and systems for temperature control for a substrate | Apr 11, 2024 | Issued |
Array
(
[id] => 19349203
[patent_doc_number] => 20240258167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 18/634809
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634809
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634809 | Methods for forming conductive vias, and associated devices and systems | Apr 11, 2024 | Issued |
Array
(
[id] => 19349203
[patent_doc_number] => 20240258167
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 18/634809
[patent_app_country] => US
[patent_app_date] => 2024-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4682
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634809
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/634809 | Methods for forming conductive vias, and associated devices and systems | Apr 11, 2024 | Issued |
Array
(
[id] => 19321345
[patent_doc_number] => 20240242892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => CAPACITOR ELEMENT, MODULE, AND SEMICONDUCTOR COMPOSITE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/618058
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618058
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618058 | Capacitor element, module, and semiconductor composite device | Mar 26, 2024 | Issued |
Array
(
[id] => 19321345
[patent_doc_number] => 20240242892
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => CAPACITOR ELEMENT, MODULE, AND SEMICONDUCTOR COMPOSITE DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/618058
[patent_app_country] => US
[patent_app_date] => 2024-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618058
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/618058 | Capacitor element, module, and semiconductor composite device | Mar 26, 2024 | Issued |
Array
(
[id] => 20080831
[patent_doc_number] => 12354908
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-08
[patent_title] => Amorphous layers for reducing copper diffusion and method forming same
[patent_app_type] => utility
[patent_app_number] => 18/609908
[patent_app_country] => US
[patent_app_date] => 2024-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 2344
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609908
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/609908 | Amorphous layers for reducing copper diffusion and method forming same | Mar 18, 2024 | Issued |
Array
(
[id] => 19161053
[patent_doc_number] => 20240153760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/417555
[patent_app_country] => US
[patent_app_date] => 2024-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12631
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18417555
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/417555 | Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium | Jan 18, 2024 | Issued |
Array
(
[id] => 20469488
[patent_doc_number] => 12525531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-13
[patent_title] => Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
[patent_app_type] => utility
[patent_app_number] => 18/407517
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 4340
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407517
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407517 | PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA | Jan 8, 2024 | Issued |
Array
(
[id] => 20469488
[patent_doc_number] => 12525531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-13
[patent_title] => Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
[patent_app_type] => utility
[patent_app_number] => 18/407517
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 4340
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407517
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407517 | PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA | Jan 8, 2024 | Issued |