Michael D. Yaary

Array ( [id] => 20481591 [patent_doc_number] => 12530066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-20 [patent_title] => Multi-power flow integrated parallel quantum computing method, system, and storage medium of power system [patent_app_type] => utility [patent_app_number] => 19/050151 [patent_app_country] => US [patent_app_date] => 2025-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 626 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19050151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20454924 [patent_doc_number] => 12517978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Curvature-based signal segmentation method for solar-blind ultraviolet photodetectors [patent_app_type] => utility [patent_app_number] => 19/031258 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1142 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19031258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20388068 [patent_doc_number] => 12487794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Processing with compact arithmetic processing element [patent_app_type] => utility [patent_app_number] => 19/021645 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12214 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19021645 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20017923 [patent_doc_number] => 20250156145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => PROCESSING WITH COMPACT ARITHMETIC PROCESSING ELEMENT [patent_app_type] => utility [patent_app_number] => 19/021660 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12214 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19021660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19950354 [patent_doc_number] => 12321719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => System and method for preprocessing and conditioning cosmic ray data for randomness generation [patent_app_type] => utility [patent_app_number] => 18/991130 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18991130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19911634 [patent_doc_number] => 12287844 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-04-29 [patent_title] => Matrix multiplication hardware architecture [patent_app_type] => utility [patent_app_number] => 18/896556 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19544950 [patent_doc_number] => 20240361986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SYSTOLIC ARRAY INCLUDING FUSED MULTIPLY ACCUMULATE WITH EFFICIENT PRENORMALIZATION AND EXTENDED DYNAMIC RANGE [patent_app_type] => utility [patent_app_number] => 18/767411 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19346 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514118 [patent_doc_number] => 20240345804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Floating-Point Dynamic Range Expansion [patent_app_type] => utility [patent_app_number] => 18/754921 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11260 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19686170 [patent_doc_number] => 20250004715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => MIXED-PRECISION MULTIPLY-AND-ACCUMULATION TREE STRUCTURE TO MAXIMIZE MEMORY BANDWIDTH USAGE FOR COMPUTATIONAL ACCELERATION OF GENERATIVE LARGE LANGUAGE MODEL [patent_app_type] => utility [patent_app_number] => 18/751662 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19811170 [patent_doc_number] => 12242564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Method and system for performing multi-device based inference for large language model [patent_app_type] => utility [patent_app_number] => 18/740201 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3577 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19451496 [patent_doc_number] => 20240311626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => ASYNCHRONOUS ACCUMULATOR USING LOGARITHMIC-BASED ARITHMETIC [patent_app_type] => utility [patent_app_number] => 18/674632 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18674632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20131202 [patent_doc_number] => 12373515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => Computational primitives using a matrix multiplication accelerator [patent_app_type] => utility [patent_app_number] => 18/633703 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8718 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633703 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19482360 [patent_doc_number] => 20240330402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MACHINE LEARNING ARCHITECTURE SUPPORT FOR BLOCK SPARSITY [patent_app_type] => utility [patent_app_number] => 18/626599 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19283729 [patent_doc_number] => 20240220205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => COUNTER-BASED MULTIPLICATION USING PROCESSING IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/607653 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19963795 [patent_doc_number] => 12333304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Methods for performing processing-in-memory operations, and related systems [patent_app_type] => utility [patent_app_number] => 18/582520 [patent_app_country] => US [patent_app_date] => 2024-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6345 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18582520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19235767 [patent_doc_number] => 20240192962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC) [patent_app_type] => utility [patent_app_number] => 18/444695 [patent_app_country] => US [patent_app_date] => 2024-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444695 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19538333 [patent_doc_number] => 12130886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-29 [patent_title] => Tensor automatic differentiation [patent_app_type] => utility [patent_app_number] => 18/421487 [patent_app_country] => US [patent_app_date] => 2024-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8065 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18421487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19963906 [patent_doc_number] => 12333416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Integrated circuit chip apparatus [patent_app_type] => utility [patent_app_number] => 18/404878 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 30838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20317171 [patent_doc_number] => 12455722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Floating-point decomposition circuitry with dynamic precision [patent_app_type] => utility [patent_app_number] => 18/399381 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 1183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19115279 [patent_doc_number] => 20240127029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => NEURAL NETWORK PROCESSING USING SPECIALIZED DATA REPRESENTATION [patent_app_type] => utility [patent_app_number] => 18/540669 [patent_app_country] => US [patent_app_date] => 2023-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18540669 [rel_patent_id] =>[rel_patent_doc_number] =>)