Search

Michael D. Yaary

Examiner (ID: 6937, Phone: (571)270-1249 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2183, 2193, 2182, 2151
Total Applications
1188
Issued Applications
991
Pending Applications
61
Abandoned Applications
151

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18414761 [patent_doc_number] => 11669303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Multiply-accumulate circuit [patent_app_type] => utility [patent_app_number] => 16/922591 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 77 [patent_no_of_words] => 23446 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922591
Multiply-accumulate circuit Jul 6, 2020 Issued
Array ( [id] => 16363410 [patent_doc_number] => 20200320161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => Interpolating a Sample Position Value by Interpolating Surrounding Interpolated Positions [patent_app_type] => utility [patent_app_number] => 16/905533 [patent_app_country] => US [patent_app_date] => 2020-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12436 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905533 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/905533
Interpolating a sample position value by interpolating surrounding interpolated positions Jun 17, 2020 Issued
Array ( [id] => 18638555 [patent_doc_number] => 11763162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Dynamic gradient calibration method for computing-in-memory neural network and system thereof [patent_app_type] => utility [patent_app_number] => 16/902282 [patent_app_country] => US [patent_app_date] => 2020-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902282
Dynamic gradient calibration method for computing-in-memory neural network and system thereof Jun 15, 2020 Issued
Array ( [id] => 18487101 [patent_doc_number] => 20230214447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND RECORDING MEDIUM [patent_app_type] => utility [patent_app_number] => 18/009080 [patent_app_country] => US [patent_app_date] => 2020-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18009080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/009080
DATA PROCESSING APPARATUS, DATA PROCESSING METHOD, AND RECORDING MEDIUM Jun 9, 2020 Pending
Array ( [id] => 17276492 [patent_doc_number] => 20210382690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => Enhanced Multiply Accumulate Device For Neural Networks [patent_app_type] => utility [patent_app_number] => 16/897201 [patent_app_country] => US [patent_app_date] => 2020-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4088 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16897201 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/897201
Enhanced multiply accumulate device for neural networks Jun 8, 2020 Issued
Array ( [id] => 16772650 [patent_doc_number] => 10983754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Accelerated quantized multiply-and-add operations [patent_app_type] => utility [patent_app_number] => 16/891010 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 18381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891010 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891010
Accelerated quantized multiply-and-add operations Jun 1, 2020 Issued
Array ( [id] => 16758452 [patent_doc_number] => 10977000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Partially and fully parallel normaliser [patent_app_type] => utility [patent_app_number] => 16/890926 [patent_app_country] => US [patent_app_date] => 2020-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5933 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16890926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/890926
Partially and fully parallel normaliser Jun 1, 2020 Issued
Array ( [id] => 17209403 [patent_doc_number] => 11169775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Processing with compact arithmetic processing element [patent_app_type] => utility [patent_app_number] => 16/882694 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16817 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882694
Processing with compact arithmetic processing element May 24, 2020 Issued
Array ( [id] => 16263184 [patent_doc_number] => 10754616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-08-25 [patent_title] => Processing with compact arithmetic processing element [patent_app_type] => utility [patent_app_number] => 16/882686 [patent_app_country] => US [patent_app_date] => 2020-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 16819 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882686
Processing with compact arithmetic processing element May 24, 2020 Issued
Array ( [id] => 17892172 [patent_doc_number] => 11455143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Using a low-bit-width dot product engine to sum high-bit-width numbers [patent_app_type] => utility [patent_app_number] => 16/869281 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16869281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/869281
Using a low-bit-width dot product engine to sum high-bit-width numbers May 6, 2020 Issued
Array ( [id] => 18486841 [patent_doc_number] => 20230214187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => METHOD FOR QUANTUM GENERATION OF RANDOM NUMBERS ESPECIALLY IN LOTTERIES AND GAMING AND DEVICE FOR QUANTUM GENERATION OF RANDOM NUMBERS [patent_app_type] => utility [patent_app_number] => 17/996335 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17996335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/996335
METHOD FOR QUANTUM GENERATION OF RANDOM NUMBERS ESPECIALLY IN LOTTERIES AND GAMING AND DEVICE FOR QUANTUM GENERATION OF RANDOM NUMBERS Apr 23, 2020 Pending
Array ( [id] => 16879772 [patent_doc_number] => 11029919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Internally truncated multiplier [patent_app_type] => utility [patent_app_number] => 16/852710 [patent_app_country] => US [patent_app_date] => 2020-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4051 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16852710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/852710
Internally truncated multiplier Apr 19, 2020 Issued
Array ( [id] => 16660374 [patent_doc_number] => 20210057011 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => VARIATION MITIGATION SCHEME FOR SEMI-DIGITAL MAC ARRAY WITH A 2T-2 RESISTIVE MEMORY ELEMENT BITCELL [patent_app_type] => utility [patent_app_number] => 16/847741 [patent_app_country] => US [patent_app_date] => 2020-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16847741 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/847741
Variation mitigation scheme for semi-digital mac array with a 2T-2 resistive memory element bitcell Apr 13, 2020 Issued
Array ( [id] => 16193325 [patent_doc_number] => 20200234174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => COST FUNCTION DEFORMATION IN QUANTUM APPROXIMATE OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 16/840685 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840685 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840685
Cost function deformation in quantum approximate optimization Apr 5, 2020 Issued
Array ( [id] => 19045711 [patent_doc_number] => 11934824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Methods for performing processing-in-memory operations, and related memory devices and systems [patent_app_type] => utility [patent_app_number] => 16/841222 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16841222 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/841222
Methods for performing processing-in-memory operations, and related memory devices and systems Apr 5, 2020 Issued
Array ( [id] => 16192793 [patent_doc_number] => 20200233642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => ENHANCED LOW PRECISION BINARY FLOATING-POINT FORMATTING [patent_app_type] => utility [patent_app_number] => 16/840847 [patent_app_country] => US [patent_app_date] => 2020-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840847 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840847
Enhanced low precision binary floating-point formatting Apr 5, 2020 Issued
Array ( [id] => 16470276 [patent_doc_number] => 20200371813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => PIPELINE ARCHITECTURE FOR BITWISE MULTIPLIER-ACCUMULATOR (MAC) [patent_app_type] => utility [patent_app_number] => 16/840393 [patent_app_country] => US [patent_app_date] => 2020-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16840393 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/840393
Pipeline architecture for bitwise multiplier-accumulator (MAC) Apr 4, 2020 Issued
Array ( [id] => 19045685 [patent_doc_number] => 11934798 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Counter-based multiplication using processing in memory [patent_app_type] => utility [patent_app_number] => 16/836773 [patent_app_country] => US [patent_app_date] => 2020-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11514 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16836773 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/836773
Counter-based multiplication using processing in memory Mar 30, 2020 Issued
Array ( [id] => 18591973 [patent_doc_number] => 11740870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Convolutional network hardware accelerator device, system and method [patent_app_type] => utility [patent_app_number] => 16/833353 [patent_app_country] => US [patent_app_date] => 2020-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 60 [patent_no_of_words] => 34967 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16833353 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/833353
Convolutional network hardware accelerator device, system and method Mar 26, 2020 Issued
Array ( [id] => 17861855 [patent_doc_number] => 11443013 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Pipelined pointwise convolution using per-channel convolution operations [patent_app_type] => utility [patent_app_number] => 16/826697 [patent_app_country] => US [patent_app_date] => 2020-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12168 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16826697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/826697
Pipelined pointwise convolution using per-channel convolution operations Mar 22, 2020 Issued
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