Search

Michael E. Barr

Supervisory Patent Examiner (ID: 16149, Phone: (571)272-1414 , Office: P/1711 )

Most Active Art Unit
1762
Art Unit(s)
1762, 1112, 1711, 1792
Total Applications
857
Issued Applications
630
Pending Applications
61
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19611639 [patent_doc_number] => 12160529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Reconfigurable PUF device based on fully electric field-controlled domain wall motion [patent_app_type] => utility [patent_app_number] => 18/061953 [patent_app_country] => US [patent_app_date] => 2022-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8060 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18061953 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/061953
Reconfigurable PUF device based on fully electric field-controlled domain wall motion Dec 4, 2022 Issued
Array ( [id] => 18833568 [patent_doc_number] => 20230402095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING CHALCOGENIDE [patent_app_type] => utility [patent_app_number] => 18/060884 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060884
SEMICONDUCTOR MEMORY DEVICE INCLUDING CHALCOGENIDE Nov 30, 2022 Abandoned
Array ( [id] => 19653415 [patent_doc_number] => 12175207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Multi-input multi-output first-in first-out buffer circuit that reads out multiple data flits at once, and electronic circuits having same [patent_app_type] => utility [patent_app_number] => 18/060806 [patent_app_country] => US [patent_app_date] => 2022-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7041 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18060806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/060806
Multi-input multi-output first-in first-out buffer circuit that reads out multiple data flits at once, and electronic circuits having same Nov 30, 2022 Issued
Array ( [id] => 20258815 [patent_doc_number] => 12431177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Memory device, memory module, and operating method of memory device for processing in memory [patent_app_type] => utility [patent_app_number] => 18/070741 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070741 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070741
Memory device, memory module, and operating method of memory device for processing in memory Nov 28, 2022 Issued
Array ( [id] => 19205864 [patent_doc_number] => 20240177763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => WORD LINE PUMP DEVICE OF DYNAMIC RANDOM ACCESS MEMORY CHIP AND CLAMP CIRCUIT THEREOF [patent_app_type] => utility [patent_app_number] => 17/994397 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2025 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17994397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/994397
Word line pump device of dynamic random access memory chip and clamp circuit thereof Nov 27, 2022 Issued
Array ( [id] => 20267105 [patent_doc_number] => 12438104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Apparatus and method for generating hardware-based physical unclonable functions and their use [patent_app_type] => utility [patent_app_number] => 18/070290 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1181 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18070290 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/070290
Apparatus and method for generating hardware-based physical unclonable functions and their use Nov 27, 2022 Issued
Array ( [id] => 18615517 [patent_doc_number] => 20230282254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => METHOD FOR DYNAMICALLY RESIZING INSTRUCTION MEMORY AND DATA MEMORY IN SYSTEM AND ASSOCIATED SYSTEM [patent_app_type] => utility [patent_app_number] => 17/976891 [patent_app_country] => US [patent_app_date] => 2022-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17976891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/976891
METHOD FOR DYNAMICALLY RESIZING INSTRUCTION MEMORY AND DATA MEMORY IN SYSTEM AND ASSOCIATED SYSTEM Oct 30, 2022 Abandoned
Array ( [id] => 19116151 [patent_doc_number] => 20240127901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION [patent_app_type] => utility [patent_app_number] => 17/968717 [patent_app_country] => US [patent_app_date] => 2022-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17968717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/968717
TEMPERATURE-BASED ERROR MASKING DURING MBIST OPERATION Oct 17, 2022 Pending
Array ( [id] => 18729106 [patent_doc_number] => 20230343401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD [patent_app_type] => utility [patent_app_number] => 17/954913 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954913
NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM, AND PROGRAMMING METHOD Sep 27, 2022 Pending
Array ( [id] => 18142365 [patent_doc_number] => 20230016209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR STRUCTURE AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/949280 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6344 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17949280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/949280
SEMICONDUCTOR STRUCTURE AND MEMORY Sep 20, 2022 Abandoned
Array ( [id] => 19007478 [patent_doc_number] => 20240071549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/822909 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822909
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION Aug 28, 2022 Pending
Array ( [id] => 18661002 [patent_doc_number] => 20230307015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/898363 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16824 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898363 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898363
SEMICONDUCTOR DEVICE Aug 28, 2022 Pending
Array ( [id] => 19007402 [patent_doc_number] => 20240071473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC CIRCUITRY OVERLYING MEMORY ARRAYS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/898150 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13386 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898150
MICROELECTRONIC DEVICES INCLUDING CONTROL LOGIC CIRCUITRY OVERLYING MEMORY ARRAYS, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS Aug 28, 2022 Pending
Array ( [id] => 19007452 [patent_doc_number] => 20240071523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY DEVICE AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/894838 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894838
Memory device and programming method thereof Aug 23, 2022 Issued
Array ( [id] => 18990849 [patent_doc_number] => 20240062818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/889707 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889707 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889707
MEMORY DEVICE AND OPERATING METHOD OF THE SAME Aug 16, 2022 Pending
Array ( [id] => 18182576 [patent_doc_number] => 20230043306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => TECHNIQUES FOR MEMORY ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/877210 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877210 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877210
TECHNIQUES FOR MEMORY ERROR CORRECTION Jul 28, 2022 Pending
Array ( [id] => 18630059 [patent_doc_number] => 20230288949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => REGULATOR PROVIDING SHARED CURRENT FROM MULTIPLE INPUT SUPPLIES [patent_app_type] => utility [patent_app_number] => 17/876323 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876323 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876323
Regulator providing shared current from multiple input supplies Jul 27, 2022 Issued
Array ( [id] => 19972242 [patent_doc_number] => 12340860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Indicating a status of a memory built-in self-test using a data mask inversion bit [patent_app_type] => utility [patent_app_number] => 17/815742 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13471 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815742 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815742
Indicating a status of a memory built-in self-test using a data mask inversion bit Jul 27, 2022 Issued
Array ( [id] => 18943174 [patent_doc_number] => 20240038313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => APPARATUS WITH CIRCUIT MANAGEMENT MECHANISM AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/875827 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875827 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/875827
Apparatus with circuit management mechanism and methods for operating the same Jul 27, 2022 Issued
Array ( [id] => 18169178 [patent_doc_number] => 20230035789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => DUAL-PORT SRAM [patent_app_type] => utility [patent_app_number] => 17/872445 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10728 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 640 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872445
Dual-port SRAM Jul 24, 2022 Issued
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