Search

Michael E. Barr

Supervisory Patent Examiner (ID: 16149, Phone: (571)272-1414 , Office: P/1711 )

Most Active Art Unit
1762
Art Unit(s)
1762, 1112, 1711, 1792
Total Applications
857
Issued Applications
630
Pending Applications
61
Abandoned Applications
171

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18926800 [patent_doc_number] => 20240029804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => ADAPTIVE FAIL BITS THRESHOLD NUMBER FOR ERASING NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/868956 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868956 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868956
ADAPTIVE FAIL BITS THRESHOLD NUMBER FOR ERASING NON-VOLATILE MEMORY Jul 19, 2022 Pending
Array ( [id] => 18472729 [patent_doc_number] => 20230207017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/810894 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810894
STORAGE DEVICE AND METHOD OF OPERATING STORAGE DEVICE Jul 5, 2022 Pending
Array ( [id] => 18126682 [patent_doc_number] => 20230012303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => SELECTIVE BIT LINE CLAMPING CONTROL FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM) [patent_app_type] => utility [patent_app_number] => 17/852567 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852567
Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Jun 28, 2022 Issued
Array ( [id] => 18472699 [patent_doc_number] => 20230206987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => INTEGRATED CIRCUIT STRUCTURE, MEMORY, AND INTEGRATED CIRCUIT LAYOUT [patent_app_type] => utility [patent_app_number] => 17/807751 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807751
INTEGRATED CIRCUIT STRUCTURE, MEMORY, AND INTEGRATED CIRCUIT LAYOUT Jun 19, 2022 Abandoned
Array ( [id] => 18820793 [patent_doc_number] => 20230395134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => WRITE DISTURB MITIGATION FOR NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL [patent_app_type] => utility [patent_app_number] => 17/805438 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805438 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805438
WRITE DISTURB MITIGATION FOR NON-LINEAR POLAR MATERIAL BASED MULTI-CAPACITOR BIT-CELL Jun 2, 2022 Pending
Array ( [id] => 18455876 [patent_doc_number] => 20230197157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ADAPTIVE READ-RETRY OFFSET BASED ON WORD LINE GROUPS FOR SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/741189 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11049 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741189
ADAPTIVE READ-RETRY OFFSET BASED ON WORD LINE GROUPS FOR SYSTEMS May 9, 2022 Pending
Array ( [id] => 18472725 [patent_doc_number] => 20230207013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => MEMORY DEVICE INCLUDING ROW DECODER [patent_app_type] => utility [patent_app_number] => 17/725372 [patent_app_country] => US [patent_app_date] => 2022-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7194 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17725372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/725372
MEMORY DEVICE INCLUDING ROW DECODER Apr 19, 2022 Pending
Array ( [id] => 17963755 [patent_doc_number] => 20220344336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR ELEMENT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/720925 [patent_app_country] => US [patent_app_date] => 2022-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17720925 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/720925
Semiconductor element memory device Apr 13, 2022 Issued
Array ( [id] => 17854913 [patent_doc_number] => 20220284956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => REDUCING CURRENT IN CROSSBAR ARRAY CIRCUITS UTILIZING LARGE INPUT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/656151 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656151
REDUCING CURRENT IN CROSSBAR ARRAY CIRCUITS UTILIZING LARGE INPUT RESISTANCE Mar 22, 2022 Pending
Array ( [id] => 19414508 [patent_doc_number] => 12080342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Static random access memory (SRAM) with a pre- charge assist circuit [patent_app_type] => utility [patent_app_number] => 17/698681 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698681
Static random access memory (SRAM) with a pre- charge assist circuit Mar 17, 2022 Issued
Array ( [id] => 18297933 [patent_doc_number] => 20230107619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => NON-VOLATILE MEMORY DEVICE WITH PARALLEL PROGRAMMING [patent_app_type] => utility [patent_app_number] => 17/693700 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7086 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693700
Non-volatile memory device with parallel programming Mar 13, 2022 Issued
Array ( [id] => 18631490 [patent_doc_number] => 20230290392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => 3D MEMORY STRUCTURE AND CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/694313 [patent_app_country] => US [patent_app_date] => 2022-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17694313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/694313
3D memory structure and circuit Mar 13, 2022 Issued
Array ( [id] => 18615526 [patent_doc_number] => 20230282263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SYSTEMS AND METHODS FOR READING BIT STATE IN ARRAYS OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/685478 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685478
Systems and methods for reading bit state in arrays of memory cells Mar 2, 2022 Issued
Array ( [id] => 19507624 [patent_doc_number] => 12119053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Method of programming MLC memory device and related MLC memory device [patent_app_type] => utility [patent_app_number] => 17/680264 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 2702 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680264
Method of programming MLC memory device and related MLC memory device Feb 23, 2022 Issued
Array ( [id] => 18570233 [patent_doc_number] => 20230260570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => ADAPTIVE WORD LINE CONTROL CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/673025 [patent_app_country] => US [patent_app_date] => 2022-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17673025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/673025
Adaptive word line control circuit Feb 15, 2022 Issued
Array ( [id] => 17567563 [patent_doc_number] => 20220131713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD TO UTILIZE MISMATCH SIZE TO PRODUCE ADDITIONAL STABLE BIT IN TILTING PUF [patent_app_type] => utility [patent_app_number] => 17/505788 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9331 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505788 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/505788
Method to utilize mismatch size to produce additional stable bit in tilting PUF Oct 19, 2021 Issued
Array ( [id] => 17412296 [patent_doc_number] => 20220047200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => INFORMATION PROCESSING CIRCUIT AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/402263 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402263
INFORMATION PROCESSING CIRCUIT AND INFORMATION PROCESSING METHOD Aug 12, 2021 Pending
Array ( [id] => 19972227 [patent_doc_number] => 12340845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-24 [patent_title] => Split block array for 3D NAND memory [patent_app_type] => utility [patent_app_number] => 17/343584 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343584 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343584
Split block array for 3D NAND memory Jun 8, 2021 Issued
Array ( [id] => 18183807 [patent_doc_number] => 20230044537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => RESISTIVE RANDOM ACCESS MEMORY ARRAY AND OPERATION METHOD THEREFOR, AND RESISTIVE RANDOM ACCESS MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/790369 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17790369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/790369
RESISTIVE RANDOM ACCESS MEMORY ARRAY AND OPERATION METHOD THEREFOR, AND RESISTIVE RANDOM ACCESS MEMORY CIRCUIT Dec 29, 2020 Pending
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