Michael H Caley

Array ( [id] => 4223669 [patent_doc_number] => 06078980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Regulating a data transfer time' [patent_app_type] => 1 [patent_app_number] => 9/222213 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 4658 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078980.pdf [firstpage_image] =>[orig_patent_app_number] => 222213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4208651 [patent_doc_number] => 06154803 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and arrangement for passing data between a reference chip and an external bus' [patent_app_type] => 1 [patent_app_number] => 9/216291 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5238 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154803.pdf [firstpage_image] =>[orig_patent_app_number] => 216291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4088422 [patent_doc_number] => 06070209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Delivering transactions between data buses in a computer system' [patent_app_type] => 1 [patent_app_number] => 9/196373 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5199 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/070/06070209.pdf [firstpage_image] =>[orig_patent_app_number] => 196373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970364 [patent_doc_number] => 05991843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method and system for concurrent computer transaction processing' [patent_app_type] => 1 [patent_app_number] => 9/176059 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4611 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991843.pdf [firstpage_image] =>[orig_patent_app_number] => 176059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036722 [patent_doc_number] => 05968153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Mechanism for high bandwidth DMA transfers in a PCI environment' [patent_app_type] => 1 [patent_app_number] => 9/170812 [patent_app_country] => US [patent_app_date] => 1998-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9417 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968153.pdf [firstpage_image] =>[orig_patent_app_number] => 170812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4167018 [patent_doc_number] => 06065083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Increasing I/O performance through storage of packetized operational information in local memory' [patent_app_type] => 1 [patent_app_number] => 9/138118 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065083.pdf [firstpage_image] =>[orig_patent_app_number] => 138118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932633 [patent_doc_number] => 06003101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Efficient priority queue' [patent_app_type] => 1 [patent_app_number] => 9/116327 [patent_app_country] => US [patent_app_date] => 1998-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4689 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003101.pdf [firstpage_image] =>[orig_patent_app_number] => 116327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4147211 [patent_doc_number] => 06128684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Bus bridge' [patent_app_type] => 1 [patent_app_number] => 9/106207 [patent_app_country] => US [patent_app_date] => 1998-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9989 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128684.pdf [firstpage_image] =>[orig_patent_app_number] => 106207 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4176881 [patent_doc_number] => 06105087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Event recognition by a state machine whose state is dependent upon historical information' [patent_app_type] => 1 [patent_app_number] => 9/095467 [patent_app_country] => US [patent_app_date] => 1998-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3394 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105087.pdf [firstpage_image] =>[orig_patent_app_number] => 095467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973159 [patent_doc_number] => 05978872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method and system for concurrent computer transaction processing' [patent_app_type] => 1 [patent_app_number] => 9/066526 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978872.pdf [firstpage_image] =>[orig_patent_app_number] => 066526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4236809 [patent_doc_number] => 06041416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Circuit for reducing audio amplifier noise during powering on and off' [patent_app_type] => 1 [patent_app_number] => 9/036822 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3834 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041416.pdf [firstpage_image] =>[orig_patent_app_number] => 036822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4151284 [patent_doc_number] => 06035344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Data transfer apparatus which outputs data based upon a control signal' [patent_app_type] => 1 [patent_app_number] => 9/024401 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 2529 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035344.pdf [firstpage_image] =>[orig_patent_app_number] => 024401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4166934 [patent_doc_number] => 06065077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Apparatus and method for a cache coherent shared memory multiprocessing system' [patent_app_type] => 1 [patent_app_number] => 8/986430 [patent_app_country] => US [patent_app_date] => 1997-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 160 [patent_figures_cnt] => 160 [patent_no_of_words] => 28269 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 584 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065077.pdf [firstpage_image] =>[orig_patent_app_number] => 986430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4014565 [patent_doc_number] => 05923859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus' [patent_app_type] => 1 [patent_app_number] => 8/974149 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 19160 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923859.pdf [firstpage_image] =>[orig_patent_app_number] => 974149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4194634 [patent_doc_number] => 06085269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Configurable expansion bus controller in a microprocessor-based system' [patent_app_type] => 1 [patent_app_number] => 8/961789 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9647 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085269.pdf [firstpage_image] =>[orig_patent_app_number] => 961789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057837 [patent_doc_number] => 05996079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method for indicating power-consumption status' [patent_app_type] => 1 [patent_app_number] => 8/960946 [patent_app_country] => US [patent_app_date] => 1997-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4315 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996079.pdf [firstpage_image] =>[orig_patent_app_number] => 960946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4036750 [patent_doc_number] => 05968155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Digital gate computer bus' [patent_app_type] => 1 [patent_app_number] => 8/948766 [patent_app_country] => US [patent_app_date] => 1997-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4737 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/968/05968155.pdf [firstpage_image] =>[orig_patent_app_number] => 948766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3970906 [patent_doc_number] => 05999999 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Communication control device and a communication system using the same' [patent_app_type] => 1 [patent_app_number] => 8/820309 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2562 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999999.pdf [firstpage_image] =>[orig_patent_app_number] => 820309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148600 [patent_doc_number] => 06016525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Inter-bus bridge circuit with integrated loopback capability and method for use of same' [patent_app_type] => 1 [patent_app_number] => 8/819018 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3983 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/016/06016525.pdf [firstpage_image] =>[orig_patent_app_number] => 819018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3973200 [patent_doc_number] => 05978875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Apparatus and method for scheduling use of bus' [patent_app_type] => 1 [patent_app_number] => 8/818868 [patent_app_country] => US [patent_app_date] => 1997-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 9773 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978875.pdf [firstpage_image] =>[orig_patent_app_number] => 818868 [rel_patent_id] =>[rel_patent_doc_number] =>)