Michael J Cross

Array ( [id] => 11724647 [patent_doc_number] => 09697503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-04 [patent_title] => 'Methods and systems for providing recommendations to vehicle users to handle alerts associated with the vehicle and a bidding market place for handling alerts/service of the vehicle' [patent_app_type] => utility [patent_app_number] => 14/176138 [patent_app_country] => US [patent_app_date] => 2014-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 31020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10493242 [patent_doc_number] => 20150378264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'A LITHOGRAPHY MODEL FOR THREE-DIMENSIONAL PATTERNING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/766408 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12868 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14766408 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10677414 [patent_doc_number] => 20160023558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-28 [patent_title] => 'NONCONTACT CHARGING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/774476 [patent_app_country] => US [patent_app_date] => 2013-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11596 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14774476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9437645 [patent_doc_number] => 20140115552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SYSTEMS AND METHODS FOR CORRELATED PARAMETERS IN STATISTICAL STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 14/138935 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7567 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14138935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10009759 [patent_doc_number] => 09053280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Rule optimization in lithographic imaging based on correlation of functions representing mask and predefined optical conditions' [patent_app_type] => utility [patent_app_number] => 14/108886 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10597 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9746628 [patent_doc_number] => 20140282347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'SYSTEM AND METHOD FOR STRENGTHENING OF A CIRCUIT ELEMENT TO REDUCE AN INTEGRATED CIRCUIT\'S POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 14/106374 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2625 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10052710 [patent_doc_number] => 09092590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Method for generating a topography of an FDSOI integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/105382 [patent_app_country] => US [patent_app_date] => 2013-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 7109 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14105382 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9410374 [patent_doc_number] => 20140101626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-10 [patent_title] => 'SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS' [patent_app_type] => utility [patent_app_number] => 14/101448 [patent_app_country] => US [patent_app_date] => 2013-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14101448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9365529 [patent_doc_number] => 20140075402 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'Method of Fast Analog Layout Migration' [patent_app_type] => utility [patent_app_number] => 14/082885 [patent_app_country] => US [patent_app_date] => 2013-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4811 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14082885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10406035 [patent_doc_number] => 20150291044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'CHARGE-DISCHARGE MANAGEMENT DEVICE, POWER CONDITIONER, POWER STORAGE DEVICE, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/441624 [patent_app_country] => US [patent_app_date] => 2013-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10410441 [patent_doc_number] => 20150295450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'WIRELESS POWER RECEIVING DEVICE AND POWER CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/441791 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14441791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9540374 [patent_doc_number] => 20140165021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-12 [patent_title] => 'SYSTEM AND METHODS FOR DYNAMIC MANAGEMENT OF HARDWARE RESOURCES' [patent_app_type] => utility [patent_app_number] => 14/069822 [patent_app_country] => US [patent_app_date] => 2013-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9796 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13668519 [patent_doc_number] => 10164446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Discharge circuit malfunction diagnosis device and discharge circuit malfunction diagnosis method [patent_app_type] => utility [patent_app_number] => 14/917412 [patent_app_country] => US [patent_app_date] => 2013-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7013 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9474404 [patent_doc_number] => 20140131867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTING SYSTEM, APPARATUS FOR FABRICATING SEMICONDUCTOR PACKAGE INCLUDING THE SYSTEM, AND SEMICONDUCTOR PACKAGE DESIGNED BY THE METHOD' [patent_app_type] => utility [patent_app_number] => 14/064102 [patent_app_country] => US [patent_app_date] => 2013-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9482 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14064102 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9980647 [patent_doc_number] => 09026978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-05 [patent_title] => 'Reverse interface logic model for optimizing physical hierarchy under full chip constraint' [patent_app_type] => utility [patent_app_number] => 14/062807 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4519 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14062807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9297207 [patent_doc_number] => 20140040841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 14/047396 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3330 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9934072 [patent_doc_number] => 20150082263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'MERIT-BASED CHARACTERIZATION OF ASSERTIONS IN HARDWARE DESIGN VERIFICATION' [patent_app_type] => utility [patent_app_number] => 14/031949 [patent_app_country] => US [patent_app_date] => 2013-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 13187 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14031949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9758993 [patent_doc_number] => 20140289693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SYSTEM AND METHOD FOR IMPROVED NET ROUTING' [patent_app_type] => utility [patent_app_number] => 14/029728 [patent_app_country] => US [patent_app_date] => 2013-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7688 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14029728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9386402 [patent_doc_number] => 20140089885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'ELECTRONIC CIRCUIT DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 14/028188 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14028188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9934070 [patent_doc_number] => 20150082262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'DYNAMICALLY GENERATING JOG PATCHES FOR JOG VIOLATIONS' [patent_app_type] => utility [patent_app_number] => 14/027329 [patent_app_country] => US [patent_app_date] => 2013-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6571 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14027329 [rel_patent_id] =>[rel_patent_doc_number] =>)