Search

Michael J Cross

Examiner (ID: 4148, Phone: (571)270-7549 , Office: P/3621 )

Most Active Art Unit
3621
Art Unit(s)
3621, 3682, 3681
Total Applications
232
Issued Applications
43
Pending Applications
0
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9028631 [patent_doc_number] => 08538222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Planar lightwave circuit, design method for wave propagation circuit, and computer program' [patent_app_type] => utility [patent_app_number] => 13/558120 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 54 [patent_no_of_words] => 25167 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558120 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558120
Planar lightwave circuit, design method for wave propagation circuit, and computer program Jul 24, 2012 Issued
Array ( [id] => 8504735 [patent_doc_number] => 20120304143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'Planar Lightwave Circuit, Design Method for Wave Propagation Circuit, and Computer Program' [patent_app_type] => utility [patent_app_number] => 13/558200 [patent_app_country] => US [patent_app_date] => 2012-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 25178 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13558200 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/558200
Planar lightwave circuit, design method for wave propagation circuit, and computer program Jul 24, 2012 Issued
Array ( [id] => 9543050 [patent_doc_number] => 20140167697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-19 [patent_title] => 'ELECTRIC BATTERY CHARGING INSTALLATION AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/235760 [patent_app_country] => US [patent_app_date] => 2012-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3863 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14235760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/235760
Electric battery charging installation and method Jul 19, 2012 Issued
Array ( [id] => 11262811 [patent_doc_number] => 09487095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Charging and discharging device' [patent_app_type] => utility [patent_app_number] => 14/237912 [patent_app_country] => US [patent_app_date] => 2012-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 14466 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14237912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/237912
Charging and discharging device Jul 18, 2012 Issued
Array ( [id] => 9379107 [patent_doc_number] => 08683393 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Integrated design environment for nanophotonics' [patent_app_type] => utility [patent_app_number] => 13/544134 [patent_app_country] => US [patent_app_date] => 2012-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4439 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13544134 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/544134
Integrated design environment for nanophotonics Jul 8, 2012 Issued
Array ( [id] => 9236112 [patent_doc_number] => 08601428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'System and method for use case-based thermal analysis of heuristically determined component combinations and layouts in a portable computing device' [patent_app_type] => utility [patent_app_number] => 13/537309 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 10072 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13537309 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/537309
System and method for use case-based thermal analysis of heuristically determined component combinations and layouts in a portable computing device Jun 28, 2012 Issued
Array ( [id] => 9207858 [patent_doc_number] => 20140007035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'Method and Apparatus to Perform Footprint-Based Optimization Simultaneously with Other Steps' [patent_app_type] => utility [patent_app_number] => 13/536903 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3398 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536903 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/536903
Footprint-based optimization performed simultaneously with other steps Jun 27, 2012 Issued
Array ( [id] => 11781790 [patent_doc_number] => 09390989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Enhanced modularity in heterogeneous 3D stacks' [patent_app_type] => utility [patent_app_number] => 13/535694 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6462 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535694 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535694
Enhanced modularity in heterogeneous 3D stacks Jun 27, 2012 Issued
Array ( [id] => 11765110 [patent_doc_number] => 09373557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Enhanced modularity in heterogeneous 3D stacks' [patent_app_type] => utility [patent_app_number] => 13/535675 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6427 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535675 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535675
Enhanced modularity in heterogeneous 3D stacks Jun 27, 2012 Issued
Array ( [id] => 9187239 [patent_doc_number] => 08627240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Integrated design environment for nanophotonics' [patent_app_type] => utility [patent_app_number] => 13/536163 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13536163 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/536163
Integrated design environment for nanophotonics Jun 27, 2012 Issued
Array ( [id] => 8633010 [patent_doc_number] => 08365109 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'Determining efficient buffering for multi-dimensional datastream applications' [patent_app_type] => utility [patent_app_number] => 13/535123 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 7070 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535123 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535123
Determining efficient buffering for multi-dimensional datastream applications Jun 26, 2012 Issued
Array ( [id] => 9695565 [patent_doc_number] => 08826195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Layout modification method and system' [patent_app_type] => utility [patent_app_number] => 13/530164 [patent_app_country] => US [patent_app_date] => 2012-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 6328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/530164
Layout modification method and system Jun 21, 2012 Issued
Array ( [id] => 9011904 [patent_doc_number] => 08527222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-03 [patent_title] => 'Method and apparatus for determining installation locations of a plurality of fault indicators in a power network' [patent_app_type] => utility [patent_app_number] => 13/529490 [patent_app_country] => US [patent_app_date] => 2012-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3460 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13529490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/529490
Method and apparatus for determining installation locations of a plurality of fault indicators in a power network Jun 20, 2012 Issued
Array ( [id] => 8810448 [patent_doc_number] => 08448115 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Through silicon via impedance extraction' [patent_app_type] => utility [patent_app_number] => 13/526443 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13526443 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/526443
Through silicon via impedance extraction Jun 17, 2012 Issued
Array ( [id] => 9599315 [patent_doc_number] => 20140195996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/526252 [patent_app_country] => US [patent_app_date] => 2012-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9814 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13526252 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/526252
Adaptive workload based optimizations coupled with a heterogeneous current-aware baseline design to mitigate current delivery limitations in integrated circuits Jun 17, 2012 Issued
Array ( [id] => 8686906 [patent_doc_number] => 20130055190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR CHECKING DESIGN OF PRINTED CIRCUIT BOARD LAYOUT FILE' [patent_app_type] => utility [patent_app_number] => 13/523874 [patent_app_country] => US [patent_app_date] => 2012-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1655 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13523874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/523874
Computing device and method for checking design of printed circuit board layout file Jun 13, 2012 Issued
Array ( [id] => 11222089 [patent_doc_number] => 09450439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Secondary battery system and operating method of secondary battery' [patent_app_type] => utility [patent_app_number] => 14/237909 [patent_app_country] => US [patent_app_date] => 2012-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4333 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14237909 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/237909
Secondary battery system and operating method of secondary battery Jun 12, 2012 Issued
Array ( [id] => 8566695 [patent_doc_number] => 20120329266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/494145 [patent_app_country] => US [patent_app_date] => 2012-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4541 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13494145 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/494145
Layout method and method of manufacturing semiconductor device Jun 11, 2012 Issued
Array ( [id] => 8935827 [patent_doc_number] => 08495549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Method for generating wiring pattern data' [patent_app_type] => utility [patent_app_number] => 13/483844 [patent_app_country] => US [patent_app_date] => 2012-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 40 [patent_no_of_words] => 10896 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13483844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/483844
Method for generating wiring pattern data May 29, 2012 Issued
Array ( [id] => 9444349 [patent_doc_number] => 08713485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Categorization of design rule errors' [patent_app_type] => utility [patent_app_number] => 13/482624 [patent_app_country] => US [patent_app_date] => 2012-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6980 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13482624 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/482624
Categorization of design rule errors May 28, 2012 Issued
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