Search

Michael J Cross

Examiner (ID: 4148, Phone: (571)270-7549 , Office: P/3621 )

Most Active Art Unit
3621
Art Unit(s)
3621, 3682, 3681
Total Applications
232
Issued Applications
43
Pending Applications
0
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9639847 [patent_doc_number] => 20140217957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'Supply System and Method for Supplying an Electric Load' [patent_app_type] => utility [patent_app_number] => 14/130206 [patent_app_country] => US [patent_app_date] => 2012-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5342 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14130206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/130206
Supply system and method for supplying an electric load May 24, 2012 Issued
Array ( [id] => 9096616 [patent_doc_number] => 20130275927 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'RC Corner Solutions for Double Patterning Technology' [patent_app_type] => utility [patent_app_number] => 13/479076 [patent_app_country] => US [patent_app_date] => 2012-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13479076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/479076
RC corner solutions for double patterning technology May 22, 2012 Issued
Array ( [id] => 8979113 [patent_doc_number] => 20130212544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'SYSTEM AND METHOD OF ELECTROMIGRATION MITIGATION IN STACKED IC DESIGNS' [patent_app_type] => utility [patent_app_number] => 13/477153 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6072 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477153
System and method of electromigration mitigation in stacked IC designs May 21, 2012 Issued
Array ( [id] => 8716252 [patent_doc_number] => 08402405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'System and method for correcting gate-level simulation accuracy when unknowns exist' [patent_app_type] => utility [patent_app_number] => 13/477743 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5571 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477743 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477743
System and method for correcting gate-level simulation accuracy when unknowns exist May 21, 2012 Issued
Array ( [id] => 8504731 [patent_doc_number] => 20120304139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'METHOD OF FAST ANALOG LAYOUT MIGRATION' [patent_app_type] => utility [patent_app_number] => 13/476027 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4783 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476027 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/476027
Method of fast analog layout migration May 20, 2012 Issued
Array ( [id] => 9150680 [patent_doc_number] => 20130305203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'MULTI-PASS ROUTING TO REDUCE CROSSTALK' [patent_app_type] => utility [patent_app_number] => 13/467696 [patent_app_country] => US [patent_app_date] => 2012-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2572 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13467696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/467696
Multi-pass routing to reduce crosstalk May 8, 2012 Issued
Array ( [id] => 9926472 [patent_doc_number] => 08984459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-17 [patent_title] => 'Methods and apparatus for layout verification' [patent_app_type] => utility [patent_app_number] => 13/464417 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464417 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464417
Methods and apparatus for layout verification May 3, 2012 Issued
Array ( [id] => 9133281 [patent_doc_number] => 20130293995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'NON-SEQUENTIAL MONITORING OF BATTERY CELLS IN BATTERY MONITORING SYSTEMS, AND RELATED COMPONENTS, SYSTEMS, AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/461862 [patent_app_country] => US [patent_app_date] => 2012-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7556 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461862 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461862
Non-sequential monitoring of battery cells in battery monitoring systems, and related components, systems, and methods May 1, 2012 Issued
Array ( [id] => 10867338 [patent_doc_number] => 08893068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-18 [patent_title] => 'Techniques to generate a more accurate simulation model' [patent_app_type] => utility [patent_app_number] => 13/461143 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461143 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461143
Techniques to generate a more accurate simulation model Apr 30, 2012 Issued
Array ( [id] => 9971899 [patent_doc_number] => 09018915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Battery protection circuit and method of controlling the same' [patent_app_type] => utility [patent_app_number] => 13/461320 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4089 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461320
Battery protection circuit and method of controlling the same Apr 30, 2012 Issued
Array ( [id] => 8507039 [patent_doc_number] => 20120306447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'APPARATUS FOR STABILIZING VOLTAGE OF ENERGY STORAGE' [patent_app_type] => utility [patent_app_number] => 13/461481 [patent_app_country] => US [patent_app_date] => 2012-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3380 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/461481
APPARATUS FOR STABILIZING VOLTAGE OF ENERGY STORAGE Apr 30, 2012 Abandoned
Array ( [id] => 8959162 [patent_doc_number] => 08504956 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Calculation of integrated circuit timing delay using frequency domain' [patent_app_type] => utility [patent_app_number] => 13/460814 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6537 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460814 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460814
Calculation of integrated circuit timing delay using frequency domain Apr 29, 2012 Issued
Array ( [id] => 8878905 [patent_doc_number] => 08473890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Timing error sampling generator and a method of timing testing' [patent_app_type] => utility [patent_app_number] => 13/460605 [patent_app_country] => US [patent_app_date] => 2012-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4749 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460605 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/460605
Timing error sampling generator and a method of timing testing Apr 29, 2012 Issued
Array ( [id] => 8810431 [patent_doc_number] => 08448098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Fracturing continuous photolithography masks' [patent_app_type] => utility [patent_app_number] => 13/453262 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9006 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13453262 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/453262
Fracturing continuous photolithography masks Apr 22, 2012 Issued
Array ( [id] => 10890740 [patent_doc_number] => 08914754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Database-driven cell-to-cell reticle inspection' [patent_app_type] => utility [patent_app_number] => 13/809825 [patent_app_country] => US [patent_app_date] => 2012-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2264 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13809825 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/809825
Database-driven cell-to-cell reticle inspection Apr 22, 2012 Issued
Array ( [id] => 8627061 [patent_doc_number] => 08359565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-22 [patent_title] => 'Method and apparatus for generating test patterns for use in at-speed testing' [patent_app_type] => utility [patent_app_number] => 13/439188 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3873 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439188 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439188
Method and apparatus for generating test patterns for use in at-speed testing Apr 3, 2012 Issued
Array ( [id] => 10067214 [patent_doc_number] => 09106077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Power control apparatus and power control method' [patent_app_type] => utility [patent_app_number] => 13/816582 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 12514 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/816582
Power control apparatus and power control method Mar 13, 2012 Issued
Array ( [id] => 9044352 [patent_doc_number] => 20130246990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'SYSTEM AND METHOD FOR MODELING THROUGH SILICON VIA' [patent_app_type] => utility [patent_app_number] => 13/419959 [patent_app_country] => US [patent_app_date] => 2012-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419959 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419959
System and method for modeling through silicon via Mar 13, 2012 Issued
Array ( [id] => 9630139 [patent_doc_number] => 08799833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'System and methods for converting planar design to FinFET design' [patent_app_type] => utility [patent_app_number] => 13/416907 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13903 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416907 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416907
System and methods for converting planar design to FinFET design Mar 8, 2012 Issued
Array ( [id] => 9077619 [patent_doc_number] => 08555211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Mask making with error recognition' [patent_app_type] => utility [patent_app_number] => 13/416897 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 3750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416897 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416897
Mask making with error recognition Mar 8, 2012 Issued
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