Search

Michael J Cross

Examiner (ID: 4148, Phone: (571)270-7549 , Office: P/3621 )

Most Active Art Unit
3621
Art Unit(s)
3621, 3682, 3681
Total Applications
232
Issued Applications
43
Pending Applications
0
Abandoned Applications
188

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8455177 [patent_doc_number] => 20120266123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-18 [patent_title] => 'COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/084582 [patent_app_country] => US [patent_app_date] => 2011-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5210 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13084582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/084582
COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS Apr 11, 2011 Abandoned
Array ( [id] => 8432943 [patent_doc_number] => 20120254818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA' [patent_app_type] => utility [patent_app_number] => 13/077933 [patent_app_country] => US [patent_app_date] => 2011-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15120 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13077933 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/077933
Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data Mar 30, 2011 Issued
Array ( [id] => 8060143 [patent_doc_number] => 20110246955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'METHOD, PROGRAM, AND APPARATUS FOR AIDING WIRING DESIGN' [patent_app_type] => utility [patent_app_number] => 13/075632 [patent_app_country] => US [patent_app_date] => 2011-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 104 [patent_figures_cnt] => 104 [patent_no_of_words] => 62284 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246955.pdf [firstpage_image] =>[orig_patent_app_number] => 13075632 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075632
Method, program, and apparatus for aiding wiring design Mar 29, 2011 Issued
Array ( [id] => 7694782 [patent_doc_number] => 20110231808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'PACKAGING DESIGN AIDING DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/048593 [patent_app_country] => US [patent_app_date] => 2011-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7374 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20110231808.pdf [firstpage_image] =>[orig_patent_app_number] => 13048593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/048593
Packaging design aiding device and method Mar 14, 2011 Issued
Array ( [id] => 8805039 [patent_doc_number] => 08443324 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Routing and timing using layer ranges' [patent_app_type] => utility [patent_app_number] => 13/047492 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6929 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13047492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047492
Routing and timing using layer ranges Mar 13, 2011 Issued
Array ( [id] => 8693325 [patent_doc_number] => 08392861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method of semiconductor integrated circuit device using library for estimating timing/area to place cells' [patent_app_type] => utility [patent_app_number] => 13/046752 [patent_app_country] => US [patent_app_date] => 2011-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 6674 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13046752 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/046752
Method of semiconductor integrated circuit device using library for estimating timing/area to place cells Mar 12, 2011 Issued
Array ( [id] => 7493389 [patent_doc_number] => 20110239181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 13/045422 [patent_app_country] => US [patent_app_date] => 2011-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9745 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239181.pdf [firstpage_image] =>[orig_patent_app_number] => 13045422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045422
WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM Mar 9, 2011 Abandoned
Array ( [id] => 8574908 [patent_doc_number] => 08341571 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-25 [patent_title] => 'Pattern signature' [patent_app_type] => utility [patent_app_number] => 13/042414 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3666 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042414 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042414
Pattern signature Mar 6, 2011 Issued
Array ( [id] => 6094366 [patent_doc_number] => 20110219342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Design Rule Optimization in Lithographic Imaging Based on Correlation of Functions Representing Mask and Predefined Optical Conditions' [patent_app_type] => utility [patent_app_number] => 13/042303 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20110219342.pdf [firstpage_image] =>[orig_patent_app_number] => 13042303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042303
Rule optimization in lithographic imaging based on correlation of functions representing mask and predefined optical conditions Mar 6, 2011 Issued
Array ( [id] => 8899603 [patent_doc_number] => 08479137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Apparatus and method for preventing congestive placement' [patent_app_type] => utility [patent_app_number] => 13/040512 [patent_app_country] => US [patent_app_date] => 2011-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3986 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13040512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/040512
Apparatus and method for preventing congestive placement Mar 3, 2011 Issued
Array ( [id] => 8372596 [patent_doc_number] => 20120221985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 13/037263 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10016 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13037263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/037263
METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY Feb 27, 2011 Abandoned
Array ( [id] => 8360992 [patent_doc_number] => 20120216155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/033582 [patent_app_country] => US [patent_app_date] => 2011-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1785 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13033582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/033582
CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT Feb 22, 2011 Abandoned
Array ( [id] => 8946078 [patent_doc_number] => 08499265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Circuit for detecting and preventing setup fails and the method thereof' [patent_app_type] => utility [patent_app_number] => 13/026653 [patent_app_country] => US [patent_app_date] => 2011-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2608 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026653 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/026653
Circuit for detecting and preventing setup fails and the method thereof Feb 13, 2011 Issued
Array ( [id] => 8333643 [patent_doc_number] => 20120200347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SKEWED PLACEMENT GRID FOR VERY LARGE SCALE INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 13/022913 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13022913 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/022913
Skewed placement grid for very large scale integrated circuits Feb 7, 2011 Issued
Array ( [id] => 6040783 [patent_doc_number] => 20110093832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'PRINTED CIRCUIT BOARD DESIGN SUPPORT APPARATUS, METHOD, AND PROGRAM MEDIUM THEREFOR' [patent_app_type] => utility [patent_app_number] => 12/978767 [patent_app_country] => US [patent_app_date] => 2010-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9458 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093832.pdf [firstpage_image] =>[orig_patent_app_number] => 12978767 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/978767
Printed circuit board design support apparatus, method, and recording medium storing program therefor Dec 26, 2010 Issued
Array ( [id] => 9392538 [patent_doc_number] => 08689163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Semiconductor apparatus capable of error revision using pin extension technique and design method therefor' [patent_app_type] => utility [patent_app_number] => 12/928021 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4440 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12928021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/928021
Semiconductor apparatus capable of error revision using pin extension technique and design method therefor Nov 30, 2010 Issued
Array ( [id] => 8201993 [patent_doc_number] => 20120124543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'FLIP-FLOP LIBRARY DEVELOPMENT FOR HIGH FREQUENCY DESIGNS BUILT IN AN ASIC FLOW' [patent_app_type] => utility [patent_app_number] => 12/948481 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9159 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124543.pdf [firstpage_image] =>[orig_patent_app_number] => 12948481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948481
Flip-flop library development for high frequency designs built in an ASIC flow Nov 16, 2010 Issued
Array ( [id] => 7493386 [patent_doc_number] => 20110239178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/947331 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16656 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20110239178.pdf [firstpage_image] =>[orig_patent_app_number] => 12947331 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947331
LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM Nov 15, 2010 Abandoned
Array ( [id] => 8752263 [patent_doc_number] => 08418107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Performing statistical timing analysis with non-separable statistical and deterministic variations' [patent_app_type] => utility [patent_app_number] => 12/943541 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5276 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943541
Performing statistical timing analysis with non-separable statistical and deterministic variations Nov 9, 2010 Issued
Array ( [id] => 9156926 [patent_doc_number] => 08589840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Semiconductor chip design verification device' [patent_app_type] => utility [patent_app_number] => 12/914801 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 13235 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12914801 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914801
Semiconductor chip design verification device Oct 27, 2010 Issued
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