Michael J Cross
Examiner (ID: 4148, Phone: (571)270-7549 , Office: P/3621 )
Most Active Art Unit | 3621 |
Art Unit(s) | 3621, 3682, 3681 |
Total Applications | 232 |
Issued Applications | 43 |
Pending Applications | 0 |
Abandoned Applications | 188 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 8455177
[patent_doc_number] => 20120266123
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[patent_kind] => A1
[patent_issue_date] => 2012-10-18
[patent_title] => 'COHERENT ANALYSIS OF ASYMMETRIC AGING AND STATISTICAL PROCESS VARIATION IN ELECTRONIC CIRCUITS'
[patent_app_type] => utility
[patent_app_number] => 13/084582
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Array
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[patent_doc_number] => 20120254818
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[patent_issue_date] => 2012-10-04
[patent_title] => 'METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA'
[patent_app_type] => utility
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Array
(
[id] => 8060143
[patent_doc_number] => 20110246955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-06
[patent_title] => 'METHOD, PROGRAM, AND APPARATUS FOR AIDING WIRING DESIGN'
[patent_app_type] => utility
[patent_app_number] => 13/075632
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/075632 | Method, program, and apparatus for aiding wiring design | Mar 29, 2011 | Issued |
Array
(
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[patent_issue_date] => 2011-09-22
[patent_title] => 'PACKAGING DESIGN AIDING DEVICE AND METHOD'
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Array
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[patent_title] => 'Routing and timing using layer ranges'
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Array
(
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[patent_title] => 'Method of semiconductor integrated circuit device using library for estimating timing/area to place cells'
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Array
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[patent_title] => 'WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/045422 | WIRING DESIGN METHOD AND COMPUTER-READABLE MEDIUM | Mar 9, 2011 | Abandoned |
Array
(
[id] => 8574908
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[patent_issue_date] => 2012-12-25
[patent_title] => 'Pattern signature'
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[patent_app_number] => 13/042414
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[patent_app_date] => 2011-03-07
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042414
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042414 | Pattern signature | Mar 6, 2011 | Issued |
Array
(
[id] => 6094366
[patent_doc_number] => 20110219342
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[patent_issue_date] => 2011-09-08
[patent_title] => 'Design Rule Optimization in Lithographic Imaging Based on Correlation of Functions Representing Mask and Predefined Optical Conditions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/042303 | Rule optimization in lithographic imaging based on correlation of functions representing mask and predefined optical conditions | Mar 6, 2011 | Issued |
Array
(
[id] => 8899603
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[patent_issue_date] => 2013-07-02
[patent_title] => 'Apparatus and method for preventing congestive placement'
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[patent_app_number] => 13/040512
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Array
(
[id] => 8372596
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[patent_title] => 'METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/037263 | METHOD AND SYSTEM FOR DESIGN OF A SURFACE TO BE MANUFACTURED USING CHARGED PARTICLE BEAM LITHOGRAPHY | Feb 27, 2011 | Abandoned |
Array
(
[id] => 8360992
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[patent_title] => 'CHECKING METHOD FOR MASK DESIGN OF INTEGRATED CIRCUIT'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/022913 | Skewed placement grid for very large scale integrated circuits | Feb 7, 2011 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/978767 | Printed circuit board design support apparatus, method, and recording medium storing program therefor | Dec 26, 2010 | Issued |
Array
(
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[patent_title] => 'Semiconductor apparatus capable of error revision using pin extension technique and design method therefor'
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Array
(
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[patent_title] => 'FLIP-FLOP LIBRARY DEVELOPMENT FOR HIGH FREQUENCY DESIGNS BUILT IN AN ASIC FLOW'
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Array
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Array
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Array
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