Search

Michael J. Metzger

Examiner (ID: 15061, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
559
Issued Applications
467
Pending Applications
60
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20070655 [patent_doc_number] => 20250208877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => METHOD FOR INSTRUCTION REWRITING, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/958186 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/958186
Method for instruction rewriting, electronic device, and computer-readable storage medium Nov 24, 2024 Issued
Array ( [id] => 20009547 [patent_doc_number] => 20250147769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => METHOD FOR PROCESSING INSTRUCTION, PROCESSOR, ELECTRONIC APPARATUS AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/935154 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935154 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/935154
METHOD FOR PROCESSING INSTRUCTION, PROCESSOR, ELECTRONIC APPARATUS AND STORAGE MEDIUM Oct 31, 2024 Pending
Array ( [id] => 20017966 [patent_doc_number] => 20250156188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => APPARATUS AND METHOD FOR PARALLEL PROCESSING [patent_app_type] => utility [patent_app_number] => 18/930458 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/930458
APPARATUS AND METHOD FOR PARALLEL PROCESSING Oct 28, 2024 Pending
Array ( [id] => 19891905 [patent_doc_number] => 20250117217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT [patent_app_type] => utility [patent_app_number] => 18/925482 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/925482
Systems and methods for performing instructions to convert to 16-bit floating-point format Oct 23, 2024 Issued
Array ( [id] => 19756676 [patent_doc_number] => 20250045241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid [patent_app_type] => utility [patent_app_number] => 18/922873 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/922873
Cluster-based placement and routing of memory units and compute units in a reconfigurable computing grid Oct 21, 2024 Issued
Array ( [id] => 19891914 [patent_doc_number] => 20250117226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MIXED-SOURCED DEPENDENCY CONTROL FOR VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/906205 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/906205
Mixed-sourced dependency control for vector instructions Oct 3, 2024 Issued
Array ( [id] => 20616706 [patent_doc_number] => 20260086802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE [patent_app_type] => utility [patent_app_number] => 18/897127 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/897127
SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE Sep 25, 2024 Pending
Array ( [id] => 19836562 [patent_doc_number] => 20250088348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/889148 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889148 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/889148
SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS Sep 17, 2024 Pending
Array ( [id] => 20601695 [patent_doc_number] => 20260079704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => ACCELERATING A FULLY HOMOMORPHIC ENCRYPTION (FHE) OPERATION WITH AN ON-CHIP SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/885269 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885269 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/885269
ACCELERATING A FULLY HOMOMORPHIC ENCRYPTION (FHE) OPERATION WITH AN ON-CHIP SYSTOLIC ARRAY Sep 12, 2024 Pending
Array ( [id] => 20587151 [patent_doc_number] => 20260072746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES [patent_app_type] => utility [patent_app_number] => 18/883431 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883431 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883431
ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES Sep 11, 2024 Pending
Array ( [id] => 19992573 [patent_doc_number] => 20250130795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => MEMORY DEVICE AND METHOD WITH PROCESSING-IN-MEMORY BLOCK [patent_app_type] => utility [patent_app_number] => 18/814641 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18814641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/814641
MEMORY DEVICE AND METHOD WITH PROCESSING-IN-MEMORY BLOCK Aug 25, 2024 Pending
Array ( [id] => 19617374 [patent_doc_number] => 20240403054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => LOOK-UP TABLE READ [patent_app_type] => utility [patent_app_number] => 18/805711 [patent_app_country] => US [patent_app_date] => 2024-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/805711
LOOK-UP TABLE READ Aug 14, 2024 Pending
Array ( [id] => 19617435 [patent_doc_number] => 20240403115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling Processor [patent_app_type] => utility [patent_app_number] => 18/800423 [patent_app_country] => US [patent_app_date] => 2024-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800423 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/800423
Thread Creation on Local or Remote Compute Elements by a Multi-Threaded, Self-Scheduling Processor Aug 11, 2024 Pending
Array ( [id] => 19573764 [patent_doc_number] => 20240378056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKING [patent_app_type] => utility [patent_app_number] => 18/779980 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18779980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/779980
STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME TRACKING Jul 21, 2024 Pending
Array ( [id] => 20249752 [patent_doc_number] => 20250298621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => PROCESSOR WITH ONE OR MORE PROGRESSIVE CONSERVATIVE EXECUTION MODES [patent_app_type] => utility [patent_app_number] => 18/773632 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773632 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773632
Processor with one or more progressive conservative execution modes Jul 15, 2024 Issued
Array ( [id] => 19711100 [patent_doc_number] => 20250021242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => PROCESSOR WITH HARDWARE-INTEGRATED MEMORY ACCESS PROTECTION [patent_app_type] => utility [patent_app_number] => 18/771764 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771764 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771764
PROCESSOR WITH HARDWARE-INTEGRATED MEMORY ACCESS PROTECTION Jul 11, 2024 Pending
Array ( [id] => 19544988 [patent_doc_number] => 20240362024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable Array [patent_app_type] => utility [patent_app_number] => 18/770560 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770560
Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable Array Jul 10, 2024 Pending
Array ( [id] => 20507091 [patent_doc_number] => 12541367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Processing for processors performing tasks having forward conditional branch instructions [patent_app_type] => utility [patent_app_number] => 18/769206 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18769206 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/769206
Processing for processors performing tasks having forward conditional branch instructions Jul 9, 2024 Issued
Array ( [id] => 19499201 [patent_doc_number] => 20240338219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CONFIGURING A PREFETCHER ASSOCIATED WITH A PROCESSOR CORE [patent_app_type] => utility [patent_app_number] => 18/747412 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747412
CONFIGURING A PREFETCHER ASSOCIATED WITH A PROCESSOR CORE Jun 17, 2024 Pending
Array ( [id] => 19703883 [patent_doc_number] => 12197919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-14 [patent_title] => Dynamic software interface translation for computing in a heterogeneous environment [patent_app_type] => utility [patent_app_number] => 18/744738 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13700 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744738 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744738
Dynamic software interface translation for computing in a heterogeneous environment Jun 16, 2024 Issued
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