Michael J. Metzger

Array ( [id] => 20034929 [patent_doc_number] => 20250173151 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => DATA PROCESSORS [patent_app_type] => utility [patent_app_number] => 19/038352 [patent_app_country] => US [patent_app_date] => 2025-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19038352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20027207 [patent_doc_number] => 20250165429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => MULTI-LEVEL HIERARCHICAL ROUTING MATRICES FOR PATTERN-RECOGNITION PROCESSORS [patent_app_type] => utility [patent_app_number] => 19/029952 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19029952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009581 [patent_doc_number] => 20250147803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => SYNCHRONIZING SCHEDULING TASKS WITH ATOMIC ALU [patent_app_type] => utility [patent_app_number] => 19/017668 [patent_app_country] => US [patent_app_date] => 2025-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20421791 [patent_doc_number] => 20250383876 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => DYNAMIC SOFTWARE INTERFACE TRANSLATION FOR COMPUTING IN A HETEROGENEOUS ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 19/015877 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19015877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009538 [patent_doc_number] => 20250147760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => PROCESSOR AND CONTROL METHOD FOR PROCESSOR [patent_app_type] => utility [patent_app_number] => 19/013344 [patent_app_country] => US [patent_app_date] => 2025-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19013344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181123 [patent_doc_number] => 20250265081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => SYSTEMS AND METHODS FOR COMPUTING DOT PRODUCTS OF NIBBLES IN TWO TILE OPERANDS [patent_app_type] => utility [patent_app_number] => 19/005958 [patent_app_country] => US [patent_app_date] => 2024-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19005958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20070655 [patent_doc_number] => 20250208877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => METHOD FOR INSTRUCTION REWRITING, ELECTRONIC DEVICE, AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/958186 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19819070 [patent_doc_number] => 20250077277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => NEURAL NETWORK PROCESSOR CAPABLE OF REUSING MEMORY ADDRESS VALUE [patent_app_type] => utility [patent_app_number] => 18/953180 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20009547 [patent_doc_number] => 20250147769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => METHOD FOR PROCESSING INSTRUCTION, PROCESSOR, ELECTRONIC APPARATUS AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/935154 [patent_app_country] => US [patent_app_date] => 2024-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18935154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20017966 [patent_doc_number] => 20250156188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => APPARATUS AND METHOD FOR PARALLEL PROCESSING [patent_app_type] => utility [patent_app_number] => 18/930458 [patent_app_country] => US [patent_app_date] => 2024-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18930458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891905 [patent_doc_number] => 20250117217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT [patent_app_type] => utility [patent_app_number] => 18/925482 [patent_app_country] => US [patent_app_date] => 2024-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18372 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18925482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19756676 [patent_doc_number] => 20250045241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => Cluster-Based Placement and Routing of Memory Units and Compute Units in a Reconfigurable Computing Grid [patent_app_type] => utility [patent_app_number] => 18/922873 [patent_app_country] => US [patent_app_date] => 2024-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18922873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20659187 [patent_doc_number] => 20260111230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => PROCESSOR [patent_app_type] => utility [patent_app_number] => 18/919168 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919168 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20652925 [patent_doc_number] => 20260104944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => RECONFIGURABLE AND ACCELERATED TRANSCEDENTAL FUNCTIONS [patent_app_type] => utility [patent_app_number] => 18/915190 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3392 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18915190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20601706 [patent_doc_number] => 20260079715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => Granular Source Read Scheduling for Instruction Execution [patent_app_type] => utility [patent_app_number] => 18/911522 [patent_app_country] => US [patent_app_date] => 2024-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18911522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19891914 [patent_doc_number] => 20250117226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => MIXED-SOURCED DEPENDENCY CONTROL FOR VECTOR INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/906205 [patent_app_country] => US [patent_app_date] => 2024-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18906205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20616706 [patent_doc_number] => 20260086802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-26 [patent_title] => SYNCHRONOUS HARDWARE ACCELERATOR INTERFACE [patent_app_type] => utility [patent_app_number] => 18/897127 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18897127 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20690963 [patent_doc_number] => 12621126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => SM3 hash algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 18/889148 [patent_app_country] => US [patent_app_date] => 2024-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 16895 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18889148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20601695 [patent_doc_number] => 20260079704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => ACCELERATING A FULLY HOMOMORPHIC ENCRYPTION (FHE) OPERATION WITH AN ON-CHIP SYSTOLIC ARRAY [patent_app_type] => utility [patent_app_number] => 18/885269 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20587151 [patent_doc_number] => 20260072746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => ADAPTIVE ARCHITECTURE FOR NEAR-MEMORY COMPUTING SHARING INACTIVE IN-MEMORY COMPUTING DEVICES [patent_app_type] => utility [patent_app_number] => 18/883431 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883431 [rel_patent_id] =>[rel_patent_doc_number] =>)