Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17108211 [patent_doc_number] => 11128443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-21 [patent_title] => SM3 hash algorithm acceleration processors, methods, systems, and instructions [patent_app_type] => utility [patent_app_number] => 17/092133 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 18993 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 439 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092133
SM3 hash algorithm acceleration processors, methods, systems, and instructions Nov 5, 2020 Issued
Array ( [id] => 16690551 [patent_doc_number] => 20210073029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => SYNCHRONIZING SCHEDULING TASKS WITH ATOMIC ALU [patent_app_type] => utility [patent_app_number] => 17/087837 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087837 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087837
Synchronizing scheduling tasks with atomic ALU Nov 2, 2020 Issued
Array ( [id] => 19780045 [patent_doc_number] => 12229078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Neural processing unit synchronization systems and methods [patent_app_type] => utility [patent_app_number] => 18/006845 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18006845 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/006845
Neural processing unit synchronization systems and methods Nov 1, 2020 Issued
Array ( [id] => 16887460 [patent_doc_number] => 20210173657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Pipelines for Secure Multithread Execution [patent_app_type] => utility [patent_app_number] => 17/081074 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9289 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081074
Pipelines for secure multithread execution Oct 26, 2020 Issued
Array ( [id] => 17999534 [patent_doc_number] => 11500641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Devices, methods, and media for efficient data dependency management for in-order issue processors [patent_app_type] => utility [patent_app_number] => 17/065501 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12010 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065501
Devices, methods, and media for efficient data dependency management for in-order issue processors Oct 6, 2020 Issued
Array ( [id] => 18015076 [patent_doc_number] => 11507372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Processing of instructions fetched from memory [patent_app_type] => utility [patent_app_number] => 17/064983 [patent_app_country] => US [patent_app_date] => 2020-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9549 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 492 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064983 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064983
Processing of instructions fetched from memory Oct 6, 2020 Issued
Array ( [id] => 19626091 [patent_doc_number] => 12164924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-10 [patent_title] => Compression metadata assisted computation [patent_app_type] => utility [patent_app_number] => 17/033308 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033308 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033308
Compression metadata assisted computation Sep 24, 2020 Issued
Array ( [id] => 16722163 [patent_doc_number] => 20210089310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => MULTIPROCESSOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/015642 [patent_app_country] => US [patent_app_date] => 2020-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17015642 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/015642
MULTIPROCESSOR DEVICE Sep 8, 2020 Abandoned
Array ( [id] => 17238280 [patent_doc_number] => 11182159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Vector reductions using shared scratchpad memory [patent_app_type] => utility [patent_app_number] => 17/007569 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13270 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007569
Vector reductions using shared scratchpad memory Aug 30, 2020 Issued
Array ( [id] => 17744310 [patent_doc_number] => 11392377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => System-on-chip, data processing method thereof, and neural network device [patent_app_type] => utility [patent_app_number] => 17/007178 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7390 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007178 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007178
System-on-chip, data processing method thereof, and neural network device Aug 30, 2020 Issued
Array ( [id] => 17288215 [patent_doc_number] => 11204765 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-12-21 [patent_title] => Deferred GPR allocation for texture/load instruction block [patent_app_type] => utility [patent_app_number] => 17/003600 [patent_app_country] => US [patent_app_date] => 2020-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003600 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/003600
Deferred GPR allocation for texture/load instruction block Aug 25, 2020 Issued
Array ( [id] => 17572820 [patent_doc_number] => 11321088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Tracking load and store instructions and addresses in an out-of-order processor [patent_app_type] => utility [patent_app_number] => 17/002378 [patent_app_country] => US [patent_app_date] => 2020-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 13770 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17002378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/002378
Tracking load and store instructions and addresses in an out-of-order processor Aug 24, 2020 Issued
Array ( [id] => 17415776 [patent_doc_number] => 20220050680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => TRACKING LOAD AND STORE INSTRUCTIONS AND ADDRESSES IN AN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/994070 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994070 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994070
Tracking load and store instructions and addresses in an out-of-order processor Aug 13, 2020 Issued
Array ( [id] => 17401567 [patent_doc_number] => 20220043657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SYSTEM AND METHOD FOR CONVOLVING IMAGE WITH SPARSE KERNELS [patent_app_type] => utility [patent_app_number] => 16/987371 [patent_app_country] => US [patent_app_date] => 2020-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10365 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16987371 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/987371
System and method for convolving image with sparse kernels Aug 5, 2020 Issued
Array ( [id] => 16454625 [patent_doc_number] => 20200364051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDTH VLIW PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/922885 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922885 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/922885
System and method of VLIW instruction processing using reduced-width VLIW processor Jul 6, 2020 Issued
Array ( [id] => 17338057 [patent_doc_number] => 20220004388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => COMMAND-AWARE HARDWARE ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/921165 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12944 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/921165
Command-aware hardware architecture Jul 5, 2020 Issued
Array ( [id] => 17622029 [patent_doc_number] => 11341085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Low energy accelerator processor architecture with short parallel instruction word [patent_app_type] => utility [patent_app_number] => 16/920901 [patent_app_country] => US [patent_app_date] => 2020-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9858 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920901
Low energy accelerator processor architecture with short parallel instruction word Jul 5, 2020 Issued
Array ( [id] => 16393257 [patent_doc_number] => 20200334198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => VECTOR REDUCTION PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/918448 [patent_app_country] => US [patent_app_date] => 2020-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16918448 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/918448
Vector reduction processor Jun 30, 2020 Issued
Array ( [id] => 17589480 [patent_doc_number] => 11327753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Processor instructions to accelerate FEC encoding and decoding [patent_app_type] => utility [patent_app_number] => 16/907715 [patent_app_country] => US [patent_app_date] => 2020-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 13768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16907715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/907715
Processor instructions to accelerate FEC encoding and decoding Jun 21, 2020 Issued
Array ( [id] => 18119188 [patent_doc_number] => 11550582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Method and apparatus to process SHA-2 secure hashing algorithm [patent_app_type] => utility [patent_app_number] => 16/903542 [patent_app_country] => US [patent_app_date] => 2020-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 30 [patent_no_of_words] => 19547 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/903542
Method and apparatus to process SHA-2 secure hashing algorithm Jun 16, 2020 Issued
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