Michael J. Metzger

Array ( [id] => 18316909 [patent_doc_number] => 11630991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Broadcasting mode of planar engine for neural processor [patent_app_type] => utility [patent_app_number] => 16/781824 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 15063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16781824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16864490 [patent_doc_number] => 11023230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof [patent_app_type] => utility [patent_app_number] => 16/747477 [patent_app_country] => US [patent_app_date] => 2020-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 17689 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16192815 [patent_doc_number] => 20200233664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => EFFICIENT RANGE-BASED MEMORY WRITEBACK TO IMPROVE HOST TO DEVICE COMMUNICATION FOR OPTIMAL POWER AND PERFORMANCE [patent_app_type] => utility [patent_app_number] => 16/717258 [patent_app_country] => US [patent_app_date] => 2019-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10967 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16717258 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18015074 [patent_doc_number] => 11507370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method and device for dynamically adjusting decimal point positions in neural network computations [patent_app_type] => utility [patent_app_number] => 16/715062 [patent_app_country] => US [patent_app_date] => 2019-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 27694 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16715062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17252845 [patent_doc_number] => 11188334 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Obsoleting values stored in registers in a processor based on processing obsolescent register-encoded instructions [patent_app_type] => utility [patent_app_number] => 16/699808 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 12272 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16699808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15715891 [patent_doc_number] => 20200104713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/698979 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15744199 [patent_doc_number] => 20200110988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => COMPUTING DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 16/698976 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18087721 [patent_doc_number] => 11537858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Computing device and method [patent_app_type] => utility [patent_app_number] => 16/698988 [patent_app_country] => US [patent_app_date] => 2019-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 6711 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16698988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16856843 [patent_doc_number] => 20210157588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => DEDICATED VECTOR SUB-PROCESSOR SYSTEM [patent_app_type] => utility [patent_app_number] => 16/697660 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4593 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697660 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16077361 [patent_doc_number] => 20200192667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => ARITHMETIC PROCESSING DEVICE, AND CONTROL METHOD FOR ARITHMETIC PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 16/697256 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697256 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18547001 [patent_doc_number] => 11720353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Processing apparatus and processing method [patent_app_type] => utility [patent_app_number] => 16/697637 [patent_app_country] => US [patent_app_date] => 2019-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4461 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16697637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15773973 [patent_doc_number] => 20200118004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => DATA SHARING SYSTEM AND DATA SHARING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 16/694176 [patent_app_country] => US [patent_app_date] => 2019-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16694176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18934450 [patent_doc_number] => 11886884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Branch prediction based on coherence operations in processors [patent_app_type] => utility [patent_app_number] => 16/680907 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 42 [patent_no_of_words] => 28830 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18430684 [patent_doc_number] => 11675906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Simultaneous multi-processor (SiMulPro) apparatus, simultaneous transmit and receive (STAR) apparatus, DRAM interface apparatus, and associated methods [patent_app_type] => utility [patent_app_number] => 16/680899 [patent_app_country] => US [patent_app_date] => 2019-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 89 [patent_no_of_words] => 13162 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16680899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18414876 [patent_doc_number] => 11669418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-06 [patent_title] => Simultaneous multi-processor apparatus applicable to achieving exascale performance for algorithms and program systems [patent_app_type] => utility [patent_app_number] => 16/674083 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 114 [patent_no_of_words] => 32296 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16674083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15561495 [patent_doc_number] => 20200065159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => DYNAMIC THREAD STATUS RETRIEVAL USING INTER-THREAD COMMUNICATION [patent_app_type] => utility [patent_app_number] => 16/673998 [patent_app_country] => US [patent_app_date] => 2019-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10226 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16673998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17091576 [patent_doc_number] => 11119765 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-14 [patent_title] => Processor with processing cores each including arithmetic unit array [patent_app_type] => utility [patent_app_number] => 16/671428 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16363138 [patent_doc_number] => 20200319889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => SPECULATIVE INSTRUCTION WAKEUP TO TOLERATE DRAINING DELAY OF MEMORY ORDERING VIOLATION CHECK BUFFERS [patent_app_type] => utility [patent_app_number] => 16/671097 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16794770 [patent_doc_number] => 20210124587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => METHODS AND APPARATUS FOR HANDLING PROCESSOR LOAD INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 16/662418 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16794769 [patent_doc_number] => 20210124586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => APPARATUS AND METHOD FOR HANDLING INCORRECT BRANCH DIRECTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 16/662438 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16662438 [rel_patent_id] =>[rel_patent_doc_number] =>)