Search

Michael J. Metzger

Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
577
Issued Applications
477
Pending Applications
65
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16802331 [patent_doc_number] => 10997276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Apparatus and methods for vector operations [patent_app_type] => utility [patent_app_number] => 16/172432 [patent_app_country] => US [patent_app_date] => 2018-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6662 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16172432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/172432
Apparatus and methods for vector operations Oct 25, 2018 Issued
Array ( [id] => 16307317 [patent_doc_number] => 10776109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Microprocessor with dynamically adjustable bit width for processing data [patent_app_type] => utility [patent_app_number] => 16/163805 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11014 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163805
Microprocessor with dynamically adjustable bit width for processing data Oct 17, 2018 Issued
Array ( [id] => 15106991 [patent_doc_number] => 10474822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Simultaneous multi-processor (SiMulPro) apparatus, simultaneous transmit and receive (STAR) apparatus, DRAM interface apparatus, and associated methods [patent_app_type] => utility [patent_app_number] => 16/154293 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 89 [patent_no_of_words] => 13033 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154293 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154293
Simultaneous multi-processor (SiMulPro) apparatus, simultaneous transmit and receive (STAR) apparatus, DRAM interface apparatus, and associated methods Oct 7, 2018 Issued
Array ( [id] => 14235425 [patent_doc_number] => 20190129885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => PROCESSOR AND CONTROL METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 16/143922 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12298 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143922
Processor and control methods thereof for performing deep learning Sep 26, 2018 Issued
Array ( [id] => 13797511 [patent_doc_number] => 20190012294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => VECTOR REDUCTION PROCESSOR [patent_app_type] => utility [patent_app_number] => 16/129663 [patent_app_country] => US [patent_app_date] => 2018-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129663
Vector reduction processor Sep 11, 2018 Issued
Array ( [id] => 15952735 [patent_doc_number] => 10664275 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Speeding up younger store instruction execution after a sync instruction [patent_app_type] => utility [patent_app_number] => 16/117058 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10425 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117058
Speeding up younger store instruction execution after a sync instruction Aug 29, 2018 Issued
Array ( [id] => 15500525 [patent_doc_number] => 20200050451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => ROBUST, EFFICIENT MULTIPROCESSOR-COPROCESSOR INTERFACE [patent_app_type] => utility [patent_app_number] => 16/101247 [patent_app_country] => US [patent_app_date] => 2018-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38016 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101247 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101247
Robust, efficient multiprocessor-coprocessor interface Aug 9, 2018 Issued
Array ( [id] => 17729476 [patent_doc_number] => 11385863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Adjustable precision for multi-stage compute processes [patent_app_type] => utility [patent_app_number] => 16/052218 [patent_app_country] => US [patent_app_date] => 2018-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16052218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/052218
Adjustable precision for multi-stage compute processes Jul 31, 2018 Issued
Array ( [id] => 16494328 [patent_doc_number] => 10860370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Synchronizing scheduling tasks with atomic ALU [patent_app_type] => utility [patent_app_number] => 16/010813 [patent_app_country] => US [patent_app_date] => 2018-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16068 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/010813
Synchronizing scheduling tasks with atomic ALU Jun 17, 2018 Issued
Array ( [id] => 13432525 [patent_doc_number] => 20180267805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => HANDLING STALLING EVENT FOR MULTIPLE THREAD PIPELINE, AND TRIGGERING ACTION BASED ON INFORMATION ACCESS DELAY [patent_app_type] => utility [patent_app_number] => 15/987113 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987113
Handling stalling event for multiple thread pipeline, and triggering action based on information access delay May 22, 2018 Issued
Array ( [id] => 13830675 [patent_doc_number] => 20190018822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => Method and Apparatus for Constructing Multivalued Microprocessor [patent_app_type] => utility [patent_app_number] => 15/984518 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984518
Method and apparatus for constructing multivalued microprocessor May 20, 2018 Issued
Array ( [id] => 15151783 [patent_doc_number] => 20190354369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES [patent_app_type] => utility [patent_app_number] => 15/979627 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9998 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979627 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979627
COMPUTING ARCHITECTURE TO PROVIDE SIMPLIFIED POST-SILICON DEBUGGING CAPABILITIES May 14, 2018 Abandoned
Array ( [id] => 15151787 [patent_doc_number] => 20190354371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => DENTIFYING AND TRACKING FREQUENTLY ACCESSED REGISTERS IN A PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/979657 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15979657 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/979657
Identifying and tracking frequently accessed registers in a processor May 14, 2018 Issued
Array ( [id] => 13568961 [patent_doc_number] => 20180336028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 15/980115 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15980115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/980115
PROCESSING DEVICE AND CONTROL METHOD OF PROCESSING DEVICE May 14, 2018 Abandoned
Array ( [id] => 16651950 [patent_doc_number] => 10929127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Systems, methods, and apparatuses utilizing an elastic floating-point number [patent_app_type] => utility [patent_app_number] => 15/973816 [patent_app_country] => US [patent_app_date] => 2018-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 16771 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15973816 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/973816
Systems, methods, and apparatuses utilizing an elastic floating-point number May 7, 2018 Issued
Array ( [id] => 17636784 [patent_doc_number] => 11347508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Apparatus and method for managing a capability domain [patent_app_type] => utility [patent_app_number] => 16/607462 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10113 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607462 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607462
Apparatus and method for managing a capability domain Apr 26, 2018 Issued
Array ( [id] => 15670415 [patent_doc_number] => 10599437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Managing obscured branch prediction information [patent_app_type] => utility [patent_app_number] => 15/963243 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9005 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15963243 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/963243
Managing obscured branch prediction information Apr 25, 2018 Issued
Array ( [id] => 15805583 [patent_doc_number] => 20200125934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MICROTHREADING FOR ACCELERATED DEEP LEARNING [patent_app_type] => utility [patent_app_number] => 16/603950 [patent_app_country] => US [patent_app_date] => 2018-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -41 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603950 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603950
Microthreading for accelerated deep learning Apr 16, 2018 Issued
Array ( [id] => 13497191 [patent_doc_number] => 20180300138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => HUMAN-MACHINE-INTERFACE SYSTEM [patent_app_type] => utility [patent_app_number] => 15/943926 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943926 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943926
Human-machine-interface system comprising a convolutional neural network hardware accelerator Apr 2, 2018 Issued
Array ( [id] => 15788871 [patent_doc_number] => 10628160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Selective poisoning of data during runahead [patent_app_type] => utility [patent_app_number] => 15/943509 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6795 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943509
Selective poisoning of data during runahead Apr 1, 2018 Issued
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