Search

Michael J. Metzger

Examiner (ID: 18687, Phone: (571)272-3105 , Office: P/2182 )

Most Active Art Unit
2182
Art Unit(s)
2182, 2183
Total Applications
547
Issued Applications
451
Pending Applications
73
Abandoned Applications
48

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19362830 [patent_doc_number] => 20240264864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => NEURAL PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/625236 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 55441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625236 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625236
NEURAL PROCESSING UNIT Apr 2, 2024 Pending
Array ( [id] => 19476014 [patent_doc_number] => 12106108 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-10-01 [patent_title] => Systems and methods for creating determinations systems [patent_app_type] => utility [patent_app_number] => 18/623567 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13401 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623567 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623567
Systems and methods for creating determinations systems Mar 31, 2024 Issued
Array ( [id] => 20281697 [patent_doc_number] => 20250306939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR OUT-OF-ORDER TASK RESOLUTION IN INTEGRATED CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/620948 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620948 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620948
APPARATUSES, SYSTEMS, AND METHODS FOR OUT-OF-ORDER TASK RESOLUTION IN INTEGRATED CIRCUITS Mar 27, 2024 Pending
Array ( [id] => 19362941 [patent_doc_number] => 20240264975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Reconfigurable Parallel Processing [patent_app_type] => utility [patent_app_number] => 18/619382 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -185 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18619382 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/619382
Reconfigurable Parallel Processing Mar 27, 2024 Pending
Array ( [id] => 20281699 [patent_doc_number] => 20250306941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => AUTOMATIC HARDWARE SPECULATION SUPPRESSION [patent_app_type] => utility [patent_app_number] => 18/620068 [patent_app_country] => US [patent_app_date] => 2024-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3433 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18620068 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/620068
AUTOMATIC HARDWARE SPECULATION SUPPRESSION Mar 27, 2024 Pending
Array ( [id] => 19466337 [patent_doc_number] => 20240320007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DATA PROCESSING DEVICE [patent_app_type] => utility [patent_app_number] => 18/612252 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612252
DATA PROCESSING DEVICE Mar 20, 2024 Pending
Array ( [id] => 19267552 [patent_doc_number] => 20240211255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => ROBUST, EFFICIENT MULTIPROCESSOR-COPROCESSOR INTERFACE [patent_app_type] => utility [patent_app_number] => 18/596106 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596106
ROBUST, EFFICIENT MULTIPROCESSOR-COPROCESSOR INTERFACE Mar 4, 2024 Pending
Array ( [id] => 20415795 [patent_doc_number] => 12499081 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Vector reduction processor [patent_app_type] => utility [patent_app_number] => 18/429142 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429142 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/429142
VECTOR REDUCTION PROCESSOR Jan 30, 2024 Issued
Array ( [id] => 19160051 [patent_doc_number] => 20240152758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => NEURAL NETWORK ACTIVATION COMPRESSION WITH NON-UNIFORM MANTISSAS [patent_app_type] => utility [patent_app_number] => 18/415159 [patent_app_country] => US [patent_app_date] => 2024-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18415159 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/415159
Neural network activation compression with non-uniform mantissas Jan 16, 2024 Issued
Array ( [id] => 19747842 [patent_doc_number] => 20250036407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => INTER-PROCESS SERVING OF MACHINE LEARNING FEATURES FROM MAPPED MEMORY FOR MACHINE LEARNING MODELS [patent_app_type] => utility [patent_app_number] => 18/413776 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413776
Inter-process serving of machine learning features from mapped memory for machine learning models Jan 15, 2024 Issued
Array ( [id] => 19747842 [patent_doc_number] => 20250036407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => INTER-PROCESS SERVING OF MACHINE LEARNING FEATURES FROM MAPPED MEMORY FOR MACHINE LEARNING MODELS [patent_app_type] => utility [patent_app_number] => 18/413776 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413776 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413776
Inter-process serving of machine learning features from mapped memory for machine learning models Jan 15, 2024 Issued
Array ( [id] => 20095022 [patent_doc_number] => 20250224958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ENCODING AND DECODING VARIABLE LENGTH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/406527 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406527
ENCODING AND DECODING VARIABLE LENGTH INSTRUCTIONS Jan 7, 2024 Pending
Array ( [id] => 20095022 [patent_doc_number] => 20250224958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ENCODING AND DECODING VARIABLE LENGTH INSTRUCTIONS [patent_app_type] => utility [patent_app_number] => 18/406527 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406527
ENCODING AND DECODING VARIABLE LENGTH INSTRUCTIONS Jan 7, 2024 Pending
Array ( [id] => 19144544 [patent_doc_number] => 20240143457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => HIGH PERFORMANCE PROCESSOR FOR LOW-WAY AND HIGH-LATENCY MEMORY INSTANCES [patent_app_type] => utility [patent_app_number] => 18/406346 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406346 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/406346
High performance processor for low-way and high-latency memory instances Jan 7, 2024 Issued
Array ( [id] => 19979215 [patent_doc_number] => 12346692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Computer processor for higher precision computations using a mixed-precision decomposition of operations [patent_app_type] => utility [patent_app_number] => 18/402606 [patent_app_country] => US [patent_app_date] => 2024-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 38 [patent_no_of_words] => 21044 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18402606 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/402606
Computer processor for higher precision computations using a mixed-precision decomposition of operations Jan 1, 2024 Issued
Array ( [id] => 19934045 [patent_doc_number] => 12307250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Systems and methods for performing 16-bit floating-point matrix dot product instructions [patent_app_type] => utility [patent_app_number] => 18/397664 [patent_app_country] => US [patent_app_date] => 2023-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 47 [patent_no_of_words] => 19684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18397664 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/397664
Systems and methods for performing 16-bit floating-point matrix dot product instructions Dec 26, 2023 Issued
Array ( [id] => 19084735 [patent_doc_number] => 20240111536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => DATA PROCESSING APPARATUS AND RELATED PRODUCTS [patent_app_type] => utility [patent_app_number] => 18/531734 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 77457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531734 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531734
Data processing apparatus and related products Dec 6, 2023 Issued
Array ( [id] => 20403492 [patent_doc_number] => 12493465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Vector load store operations in a vector pipeline using a single operation in a load store unit [patent_app_type] => utility [patent_app_number] => 18/524222 [patent_app_country] => US [patent_app_date] => 2023-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18524222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/524222
Vector load store operations in a vector pipeline using a single operation in a load store unit Nov 29, 2023 Issued
Array ( [id] => 20034923 [patent_doc_number] => 20250173145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => FILTERING BRANCH INSTRUCTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 18/520983 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520983
FILTERING BRANCH INSTRUCTION PREDICTIONS Nov 27, 2023 Pending
Array ( [id] => 20034923 [patent_doc_number] => 20250173145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => FILTERING BRANCH INSTRUCTION PREDICTIONS [patent_app_type] => utility [patent_app_number] => 18/520983 [patent_app_country] => US [patent_app_date] => 2023-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18520983 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/520983
FILTERING BRANCH INSTRUCTION PREDICTIONS Nov 27, 2023 Pending
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