
Michael J. Metzger
Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183 |
| Total Applications | 577 |
| Issued Applications | 477 |
| Pending Applications | 65 |
| Abandoned Applications | 48 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 18/846638 | TIME-DIVISION MULTIPLEXED SIMD FUNCTION UNIT | Sep 11, 2024 | Pending |
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