
Michael J. Metzger
Examiner (ID: 19567, Phone: (571)272-3105 , Office: P/2182 )
| Most Active Art Unit | 2182 |
| Art Unit(s) | 2182, 2183 |
| Total Applications | 577 |
| Issued Applications | 477 |
| Pending Applications | 65 |
| Abandoned Applications | 48 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14282053
[patent_doc_number] => 20190138311
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-09
[patent_title] => SYSTEM AND METHOD OF VLIW INSTRUCTION PROCESSING USING REDUCED-WIDTH VLIW PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/805935
[patent_app_country] => US
[patent_app_date] => 2017-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8188
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805935
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/805935 | System and method of VLIW instruction processing using reduced-width VLIW processor | Nov 6, 2017 | Issued |
Array
(
[id] => 16574461
[patent_doc_number] => 10896386
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-19
[patent_title] => Computerized branch predictions and decisions
[patent_app_type] => utility
[patent_app_number] => 15/802776
[patent_app_country] => US
[patent_app_date] => 2017-11-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6846
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802776
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/802776 | Computerized branch predictions and decisions | Nov 2, 2017 | Issued |
Array
(
[id] => 15982143
[patent_doc_number] => 10671399
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
[patent_app_type] => utility
[patent_app_number] => 15/796032
[patent_app_country] => US
[patent_app_date] => 2017-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3934
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796032
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/796032 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Oct 26, 2017 | Issued |
Array
(
[id] => 16270990
[patent_doc_number] => 20200272478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-27
[patent_title] => VECTOR PROCESSOR AND CONTROL METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 16/462086
[patent_app_country] => US
[patent_app_date] => 2017-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6861
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462086
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/462086 | Vector processor and control method therefor | Oct 22, 2017 | Issued |
Array
(
[id] => 16232729
[patent_doc_number] => 10740280
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-08-11
[patent_title] => Low energy accelerator processor architecture with short parallel instruction word
[patent_app_type] => utility
[patent_app_number] => 15/714212
[patent_app_country] => US
[patent_app_date] => 2017-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 9837
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714212
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/714212 | Low energy accelerator processor architecture with short parallel instruction word | Sep 24, 2017 | Issued |
Array
(
[id] => 15074947
[patent_doc_number] => 10466964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-11-05
[patent_title] => Engine architecture for processing finite automata
[patent_app_type] => utility
[patent_app_number] => 15/703638
[patent_app_country] => US
[patent_app_date] => 2017-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
[patent_figures_cnt] => 33
[patent_no_of_words] => 33060
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703638
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/703638 | Engine architecture for processing finite automata | Sep 12, 2017 | Issued |
Array
(
[id] => 16065011
[patent_doc_number] => 10691455
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-23
[patent_title] => Power saving branch modes in hardware
[patent_app_type] => utility
[patent_app_number] => 15/684573
[patent_app_country] => US
[patent_app_date] => 2017-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6840
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15684573
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/684573 | Power saving branch modes in hardware | Aug 22, 2017 | Issued |
Array
(
[id] => 16185996
[patent_doc_number] => 10719328
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-07-21
[patent_title] => Determining and predicting derived values used in register-indirect branching
[patent_app_type] => utility
[patent_app_number] => 15/680855
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19217
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680855
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680855 | Determining and predicting derived values used in register-indirect branching | Aug 17, 2017 | Issued |
Array
(
[id] => 15386849
[patent_doc_number] => 10534609
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-01-14
[patent_title] => Code-specific affiliated register prediction
[patent_app_type] => utility
[patent_app_number] => 15/680881
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19271
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680881
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680881 | Code-specific affiliated register prediction | Aug 17, 2017 | Issued |
Array
(
[id] => 16551588
[patent_doc_number] => 10884747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-05
[patent_title] => Prediction of an affiliated register
[patent_app_type] => utility
[patent_app_number] => 15/680871
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19201
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680871
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680871 | Prediction of an affiliated register | Aug 17, 2017 | Issued |
Array
(
[id] => 16551587
[patent_doc_number] => 10884746
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-05
[patent_title] => Determining and predicting affiliated registers based on dynamic runtime control flow analysis
[patent_app_type] => utility
[patent_app_number] => 15/680824
[patent_app_country] => US
[patent_app_date] => 2017-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 34
[patent_no_of_words] => 19213
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15680824
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/680824 | Determining and predicting affiliated registers based on dynamic runtime control flow analysis | Aug 17, 2017 | Issued |
Array
(
[id] => 17469106
[patent_doc_number] => 11275583
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-15
[patent_title] => Apparatus and method of improved insert instructions
[patent_app_type] => utility
[patent_app_number] => 15/668461
[patent_app_country] => US
[patent_app_date] => 2017-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 43
[patent_no_of_words] => 21965
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15668461
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/668461 | Apparatus and method of improved insert instructions | Aug 2, 2017 | Issued |
Array
(
[id] => 15935801
[patent_doc_number] => 20200159534
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-05-21
[patent_title] => SYSTEM AND METHOD ENABLING ONE-HOT NEURAL NETWORKS ON A MACHINE LEARNING COMPUTE PLATFORM
[patent_app_type] => utility
[patent_app_number] => 16/633071
[patent_app_country] => US
[patent_app_date] => 2017-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16633071
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/633071 | System and method enabling one-hot neural networks on a machine learning compute platform | Aug 1, 2017 | Issued |
Array
(
[id] => 15982141
[patent_doc_number] => 10671398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-02
[patent_title] => Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
[patent_app_type] => utility
[patent_app_number] => 15/666822
[patent_app_country] => US
[patent_app_date] => 2017-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3934
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15666822
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/666822 | Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core | Aug 1, 2017 | Issued |
Array
(
[id] => 16346236
[patent_doc_number] => 20200310887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-10-01
[patent_title] => METHOD FOR SYNCHRONIZED OPERATION OF MULTICORE PROCESSORS
[patent_app_type] => utility
[patent_app_number] => 16/311970
[patent_app_country] => US
[patent_app_date] => 2017-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5087
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16311970
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/311970 | Method for synchronized operation of multicore processors | May 31, 2017 | Issued |
Array
(
[id] => 13579879
[patent_doc_number] => 20180341488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-29
[patent_title] => MICROPROCESSOR INSTRUCTION PREDISPATCH BEFORE BLOCK COMMIT
[patent_app_type] => utility
[patent_app_number] => 15/606673
[patent_app_country] => US
[patent_app_date] => 2017-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16814
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606673
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/606673 | MICROPROCESSOR INSTRUCTION PREDISPATCH BEFORE BLOCK COMMIT | May 25, 2017 | Abandoned |
Array
(
[id] => 13721401
[patent_doc_number] => 20170371655
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => PROCESSOR AND CONTROL METHOD OF PROCESSOR
[patent_app_type] => utility
[patent_app_number] => 15/606097
[patent_app_country] => US
[patent_app_date] => 2017-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7146
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -3
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15606097
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/606097 | PROCESSOR AND CONTROL METHOD OF PROCESSOR | May 25, 2017 | Abandoned |
Array
(
[id] => 13569887
[patent_doc_number] => 20180336491
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => COMPUTERIZED BRANCH PREDICTIONS AND DECISIONS
[patent_app_type] => utility
[patent_app_number] => 15/599770
[patent_app_country] => US
[patent_app_date] => 2017-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6823
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15599770
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/599770 | Computerized branch predictions and decisions | May 18, 2017 | Issued |
Array
(
[id] => 13525969
[patent_doc_number] => 20180314527
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => PROCESSING OPERATION ISSUE CONTROL
[patent_app_type] => utility
[patent_app_number] => 15/497461
[patent_app_country] => US
[patent_app_date] => 2017-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15497461
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/497461 | Processing operation issue control | Apr 25, 2017 | Issued |
Array
(
[id] => 12032806
[patent_doc_number] => 20170322905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'APPARATUS AND METHOD OF MASK PERMUTE INSTRUCTIONS'
[patent_app_type] => utility
[patent_app_number] => 15/495933
[patent_app_country] => US
[patent_app_date] => 2017-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 16468
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495933
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/495933 | Apparatus and method of mask permute instructions | Apr 23, 2017 | Issued |